Description
In systems where multiple power rails are involved, timing and voltage differences during power-up and power-down can be critical issues to the power system designer. As a simple example, a single DSP with its core and I/O voltage require properly designed power sequencing to prevent the possibility of a latch-up failure or excessive current draw upon activation.

This topic addresses some of the more common sequencing requirements of DSPs, FPGAs, ASICs, and microprocessors, and proposes a variety of practical solutions. These techniques take advantage of the reset, power good, enable, and soft-start features available on many types of power management devices ranging from low drop-out (LDO) regulators to plug-in power modules.

Objective

Key Learning

Course Modules
1. Module 01(ATECH3-2)