Hi, welcome to April 2018. Today, at the Texas Instruments booth here in San Antonio, Texas, we are showing a 10 kilowatt three-level three-phase silicon carbide-based gate driver design. On this particular design, we've gone with the choice of a three-level T-type powered topology for radius ground currents as well as radius output harmonics. We've gone with a choice of silicon carbide with low RDSN for overall improved efficiency. We've gone with high switching speeds of 50 kilowatts and beyond to reduce the overall magnetics and improve the form factor.

Today, with us, we have Bart Basile, who's a system designer on this-- who is going to help us walk through some of the challenges he had putting this design together. First, we have seen that a lot of customers especially with high-power designs are looking at silicon carbide. So let me start with the most obvious question. Why silicon carbide?

Sure. So silicon carbide, it's a brand new technology that we've been seeing emerge over the last few years. And the main reason people are choosing it is because of that high electron mobility that it's bringing to the table. That lets you switch much faster like you mentioned. On this design, we're going up to 50 kilohertz, which is over double what we traditionally see inside solar inverters. In addition, these FETs are starting at 1,000 volt capabilities. The ones we're using in particular are 1,200 volts. So this high voltage rating lets us do 1,000 volt DC input with a single h-bridge for the power stage. Also, we have significantly improved thermal design on these particular devices just because of the inherent properties, so we can get the heat out of the system faster and increase system longevity.

And why three-level or T-type power topology on this one?

So the specific topology is like you said. It's a three-level T-type neutral point clamp. Because of that neutral point clamping that we get on here, we can reduce the ground currents in the system, and it also helps reduce output harmonics. So that output harmonic reduction also results in what reduced magnetic sizing. In addition, with this kind of topology, it's actually fairly easy to get the computation on it, because it's very similar to what we see in the traditional half bridge. So migrating from your half bridge design to a three-level T-type is fairly straightforward.

Fantastic. As there is a lot of TI technology on this particular design. To highlight a few, the silicon carbide MOSFETs are being driven by TI-isolated gate drivers. There are numerous places on this particular design where we are doing voltage current sensing using TI technology. And of course, the [INAUDIBLE] controlled loop on this particular system is being driven by a C2000 microcontroller from TI. Can you help us understand how we're driving the silicon carbides on this particular design here?

Yeah, I'd be happy to. So we're using the TI's ISO 58582s capacitively isolated reinforced gate drivers with a single package device with a 30 volt output swing-- just perfect for driving [INAUDIBLE] from negative five to 25 at five amps. So it's great for the FETs that we're using in this particular design or any similar style FETs that [? Maple ?] might use. In addition, it has some smart features like desat protection, which helps prevent any kind of issues with shoot-through or over-current issues on the FETs themselves to make sure that they stay robust throughout the life of the device.

And in this particular design there is a lot of places where we're doing voltage, and currents, and [INAUDIBLE]. So can you tell us where and how we are doing that?

Sure. So just like a traditional inverter, even though it's a three-level, we're measuring our input DC bus voltage, the actual inverter output voltage, and then sensing also on the grid side, so we can do synchronization. And all of this is done with TI signal chain devices like our OPA family. For the current side, we're measuring inverter current using magnetically isolated flex gate sensors. And on the output, we're actually using shunt resistors that are reinforced isolated delta sigma modulators, the AMC1306, which output a bit stream back to the MCU. So it's immune to any kind of noise in the system that normally might pop up.

Great. And last but not least, how is the digital control loop working on this particular design?

So we're using one of TI's newer Delfino series C2000 processors. It's actually a dual core DSP. And in hardware, it has accelerators for the PWM signals that are perfect match for H-Bridges in power designs like this. It also has accelerators for all of the high computation math and filters that you need inside one of these systems. And it has a lot of other hardware integrated like ADCs for the voltage sensing and the filtering for all of the isolated delta sigma modulators as well-- built into the hardware.

Fantastic. One of the key targets for us on this particular design was high efficiency and high power density, so how did we do on that particular scale in this design?

So this design actually reached over 99% efficiency in our testing, and our total power density-- since we're at 10 kilowatts for this design-- is over 1.4 kilowatts per liter.

Fantastic. Fantastic. Thank you, Bart, for your time today. For this design, TIDA 1606 as well as other silicon carbide-based designs, please visit us at ti.com/SiC. Thank you.