March 14, 2019
This is the third of three training modules that provide an introduction to the Sitara AM6x processor Flash Subsystem (FSS), which is used to interface to Octal SPI (OSPI) and HyperBus devices. This HyperBus overview takes a look at the HyperBus Memory Controller (HBMC), HyperRAM, and HyperFlash
1AM65x Sitara™ processors overview (7)
This section provides an overview of the AM65x Sitara processors for industrial application development.
2Processor SDK for our embedded processors (5)
This section provides an overview of the Processor SDK for Linux and RTOS for use on our embedded processors.
3Sitara™ processors building blocks for PRU development (1)
This series includes an overview of the PRU subsystem, device and IO integration, application design, and programming model.
4Tools for PRU development (2)
This series provides information on how to get started using the software and tools for developing PRU applications on supported processors.
5Running industrial protocols on PRU (2)
These videos introduce the PRU-ICSS protocols built on top of Processor SDK to enable real-time industrial communications for our Sitara™ embedded processors.
6AM65x Sitara™ processors flash subsystem (FSS) (3)
These training modules provide an introduction to the Sitara AM6x FSS.
7Introduction to PRU-ICSSG (3)
This section provides an overview of the PRU-ICSSG for gigabit-speed industrial subsystems.