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Control of SMPS - A refresher Control of SMPS, loop transfer functions
Control of SMPS - A refresher
Control of SMPS, loop transfer functions
Hello and welcome to part two of this three-part talk on the control of switch mode power supplies. My name is Colin Gillmor, and I'm an applications engineer with Texas Instruments based in Cork in Ireland. In part one, I covered some basic concepts-- transfer functions in general, and introduced voltage mode and current mode control. In part two, I want to look at the two main loop transfer functions-- that is, the control to output, and the output control-- and then I will look at the loop compensation strategies. Part three will cover the remaining agenda items.
Let's look at the transfer function at the power stage-- our plant, as it is sometimes called. I'm going to follow convention and call this function G of s. G of s is the transfer function from the control input VC to the system output, VOUT, and I've graphed it here for the Buck converter in voltage mode control on top and peak current mode control at the bottom.
I've identified the various poles and zeros of these transfer functions in the plots. Different power stage topologies will have different transfer functions, but the general principles are the same, so I'm going to concentrate on the Buck stage here. There are a few things worth noting in these plots. We've seen before that the Buck converter in voltage mode control has a peak at the resonant frequency of the output filter. We'd expect that this resonance, our complex conjugate pole, would give a minus 180 degree phase shift at high frequencies.
However, this phase shift is reduced a little because of the phase boost due to the zero from the ESR of the output capacitor. If you look carefully, the gain slope also reduces from minus 40 dB per decade to minus 20 dB per decade. But the most important characteristic is the phase boost. The Buck converter in peak current mode control does not have this resonance.
Technically, and if you look deeply into the maths, the addition of the current loop splits the complex conjugate poles of the voltage mode control characteristic into two real poles. You can see a low frequency pole at omega p1 and a high frequency pole at omega p2. This effectively changes the PWM modulator into a voltage controlled current source. The phase boost from the output capacitor ESR at omega Z remains and is clearly visible. Overall, peak current mode control has turned the second order characteristic of voltage mode control into a first order characteristic. This makes it much easier to stabilize and allows a higher loop bandwidth.
This plot shows the control to output transfer function of a Flyback supply. The position of the right half-plane zero, omega r, is marked, and it is clear that the minus 20 dB per decade slope due to the pole at omega p begins to reduce as the gain due to the zero increases. It increases further at the zero due to the ESR at the output capacitor at omega Z, before finally leveling off as the pole from the output inductor takes effect at omega L.
Overall, the phase has dropped by minus 180 degrees over this frequency range. The net effect of the right half-plane zero is to add gain while reducing the phase. We shall see that this significantly reduces the closed-loop control bandwidth that we can achieve.
The output to control transfer function is the second part of the overall loop. Its input is a measurement of the output of the plant-- our power stage-- and its output is a control signal which acts as a current demand signal in current mode control systems, or which is used to directly control the duty cycle in voltage mode control. For a given power stage, the characteristics of the feedback system determine the characteristics of the overall control loop, and it must have these essential characteristics.
First, it must have a 180-degree phase shift at DC for negative feedback. It must have a high gain at DC so that only a very small change in output voltage is necessary to cause VC to command duty cycles from DMIN to DMAX. It must be designed to achieve a high loop bandwidth for fast transient response-- PFC applications are an exception to this rule of course-- and the overall loop must have an adequate gain and phase margin to assure stability.
The overall loop bandwidth must be low enough to prevent the control system from seeing or being influenced by the switching action in the power stage. In practice, this means that the control loop bandwidth must be less than approximately 10% to 20% of the switching frequency. To make the system less sensitive to component variations, the loop gains should be dropping at minus 20 dB at the crossover frequency. That is the frequency where the gain is zero dB.
Now, we've got enough information to look at the compensation of the overall control loop. There are three generic types of compensation network used. These are called type one, type two, and type three and I've listed their broad characteristics here. Type one can be used if a very low controlled bandwidth is acceptable-- for example, in PFC stages or during product development where the bandwidth can be reduced to a very low level to allow the designer to verify the power stage design first and then move on to optimizing the control loop bandwidth.
Type two is mainly used in current mode control systems. Type three is used mainly in voltage mode control systems, or sometimes in current mode control systems where the zero due to the EST at the output capacitor is at too high a frequency to give adequate phase boost. The terms PI and PID are also seen, but mainly in the context of discrete time systems and digital control loops, so I'm not going to mention them any further.
I want to take a brief look at the requirements for a stable loop. Negative feedback requires that there must be 180 degree of phase shift at DC. The system will oscillate at the 0 dB crossover frequency if there is an additional 180-degree phase shift around the loop. If the system were completely linear, the oscillation will be sinusoidal, but in practice, its amplitude will be limited by system non-linearities
There is a good explanation of why this is the only frequency at which the system can become unstable in reference four. Loop stability requires that the phase must be less than 180 degrees as the gain passes through 0 dB. Remember, 0 dB corresponds to a gain of 1. Phase margin is the amount by which the phase shift at crossover is less than 180 degrees. It's about 76 degrees in this plot. It's also conventional to assume the existence of the 180-degree phase shift at DC and to not add it into the calculations are showed in the phase plot.
The gain margin is the amount by which the gain is less than 0 dB as the phase drops below 180 degree, and as I said earlier, the loop gain should be less than 0 dB before approximately 10% to 20% of the switching frequency. One thing to be avoided is a metastable condition where the gain, having dropped below 0 dB, then increases again.
Now we're in a position to put all these pieces together and to look at the complete loop response and how the compensation network is used to ensure system stability. Here, I'm going to use a Buck PSU operating under peak current mode control.
We've seen G of s previously. The plot here shows the transfer function of a Buck converter on peak current mode control. H of s is a gain phase plot of a type two compensator. It has a DC gain set by the open loop gain of the amplifier, which starts to roll off at the low frequency pole set by R1 and C1. The zero formed by R2 and C2 is placed at the frequency of about 1/10 of this crossover frequency. This flattens out the error amplifier response, while the plant gain starts to decrease.
The other main effect of this zero is to give some phase boost, which cancels out the phase drop due to the pole in the plant. R2 and C2 form a high frequency pole above which the error amplified gain decreases again. The phase starts to drop, too, as this pole takes effect. Overall, the error-amplified gain drops as frequency increases. Note that the low frequency and high frequency phase shift are both minus 90 degrees. The phase boost in the mid-range of frequencies cancels out the phase drop. The overall effect is that the gain crosses over the 0 dB line with a 76-degree phase margin and at minus 20 dB per decade.
This is a typical schematic of a type three compensator along with the Bode plot of its transfer function. A type two compensator could be used to close the loop around the plant transfer function shown here, but the loop crossover frequency would have to be significantly lower than the output resonance. Type three compensation allows a significantly higher crossover frequency because it can give up to 180 degrees of phase boost, versus the 90 degrees which a type two compensator can achieve, and this is the main justification for its use.
The low frequency pole formed by R1 and C1 has the same effect as before. There are two zeros in the network, C2 R2 and C3 R1. Both of these are usually placed at about 1/10 of the loop crossover frequency. Their main effect is to introduce a large multiphase boost which is clearly visible in the plot of H of s. The pole followed by R3 and C3 is placed at about three times the crossover frequency, and it helps to drop the loop gain.
The high frequency pole formed by R2 and C1 increases the rate at which the gain drops at high frequencies. In this case, the total loop response has a phase margin of about 90 degrees, which is probably too much because, although the system will be stable, the transient response will be over-damped. And we'll take a look at this later on in part three.
Many switch mode power supplies have an isolated output. Some low power Flyback designs are primary side regulated, but most, if not all, high power circuits use secondary side regulation with a primary side controller. This requires some method to include an isolation barrier in the feedback path. One common solution is to use a TL431 as an error amplifier and to use an optocoupler to provide the isolation barrier.
The general approach to designing a compensation network using TL431 and optocoupler is the same. The schematic here shows a type two compensation network along with its associated transfer function, H of s. The circuit has two feedback paths. The one shown in red dominates at low and medium frequencies where the error amplifier in the TL431 controls the LED current. At high frequency, the TL431 gain has dropped to a very low value, and it no longer controls the LED current. However, variations in VOUT can drive currents in the LED through the blue path, and this path actually dominates at high frequencies.
One of the main issues with this circuit is that the parasitic capacitance of the optocoupler is not very well-characterized, and it's difficult to know exactly where the HF pole appears. Typically, it's somewhere between 10 kilohertz and 20 kilohertz. Techniques do exist to eliminate this pole due to the parasitic output capacitance of the optocoupler. These work by keeping the phototransistor VCE constant so that CO has no effect. But these techniques are really beyond the scope of this talk. I just wanted to mention that they do exist.
Now, there are two main methods to implement current mode control-- peak current mode and average current mode. Both use an error amplifier to set a current demand signal, and the current loop forces the output current to match the demand current. If you're using average current mode control, then the inner current loop must be stabilized in a similar fashion to the outer voltage loop which we have been discussing up to now. Reference nine covers the stabilization of average current mode control systems, so I'm not going to go into any more detail about this here.
In peak current mode control, the stability of the current loop is not normally a problem except if operating at large duty cycles and in continuous conduction mode. Under these conditions, slope compensation is normally necessary. Peak current mode control has many advantages, but it does have an inherent instability if operated with wide duty cycles. The upper diagram shows that a small perturbation in inductor current, delta IL, will die out in a few cycles at small duty cycles. The lower diagram shows that at wide duty cycle, the same perturbation increases as time progresses.
The rule of thumb is that the system will be stable if the duty cycle is less than 50% and unstable if the duty cycle is greater than 50%. However, in practice, the boundary between stability and instability isn't quite as sharp as this, and the system becomes increasingly under-damped as the duty cycle increases past about 40%. Peak current mode control in general, including this instability, are very well explained in reference seven.
The usual solution to this sub-harmonic instability is to add a slope compensation ramp. This ramp can either be added to the signal representing the inductor current or subtracted from the error amplifier output. Here, I've shown it to be subtracted from the error amplifier output, IDM-- that is, the demand current. There are a lot of options relating to how to optimize the slope compensation ramp, and many of these are explained in reference eight. For now, I want to point out just a few things. The slope compensation ramp should be at least 50% of the inductor current downslope. This will stabilize this system out to 100% duty cycle, although recovery from perturbation takes a few cycles to accomplish.
One advantage of this level of slope compensation is that the Peak-to-Average ratio of the inductor current does not change with duty cycle. This means that the input current to a PFC stage will not be distorted as the duty cycle changes through the line cycle because the ratio between the controlled quantity-- which is the peak conductor current-- and the desired quantity-- which is the average inductor current-- does not change. If the slope compensation ramp is set to 100% of the inductor current downslope, then recovery from a perturbation happens in a single cycle. This is, obviously, desirable for best transient recovery.
Nonlinear slope compensation is also possible and does have some application in systems which have wide variations in output voltage, and slope compensation should be used if the system duty cycle is likely to exceed about 40%. Finally, the current sent signal can often contain a contribution from the magnetizing inductance of an isolation transformer. In this case, the magnetizing current adds to the current sent signal and effectively forms part of a slope compensation ramp. The ramp due to the magnetizing current may even be sufficient to eliminate the need for a separate slope compensation ramp.
And here's the list of references that you may find useful. Thanks for your attention, and I hope you found this talk useful. As before, please feel free to contact me directly at this email address if you have any questions or if you have any suggestions for improvements that I could make. Now, I invite you to take a look at part three.
April 8, 2019
In this series of videos I want to show that it is possible to gain a good qualitative understanding and feel for analog control of SMPS without using too much mathematics. I will show how a functioning Switched Mode Power Supply control system is designed and how the loop is stabilised. I will discuss the Gain Phase and Load transient test methods used to verify that a design is stable and indicated what the limits for acceptance might be.