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C2000™ digital power Deep dive on SiC based 10kW grid tied inverter design
C2000™ MCUs - Digital power
1.5 Deep dive on SiC based 10kW grid tied inverter design
Hello, and welcome to this training. Going to be a deep dive on silicon carbide base 10 kilowatt grid tie inverter design challenges. My name is Bart Basile. I'm part of the systems engineering and marketing team here at Texas Instruments, focusing on renewable energy. Hopefully today we can go through some details on why exactly we're using silicon carbide, what are some of the changes for using SiC inside an inverter, and some of the topology adjustments that we used and specific design implementations for this specific design that we did here at TI. Hopefully it can help you with your own design.
So first off, we want to take a little bit of an understanding at a high level of why silicon carbide. For many of you, the name SiC might not be very new. However, I know for many people in the audience, this material might be just something you've heard about and don't really know many details of. So hopefully we can take a moment here and look at some of the benefits of using silicon carbide, some of the challenges in the marketplace today, and why exactly we would like to use it inside solar inverter applications.
So to really get a good understanding of silicon carbide and its benefits, let's first take a little bit of a look at the intrinsic material properties. So have a few different categories here. And this chart is showing SiC compared to gallium nitride, as well as traditional silicon solutions.
So we can see here the blue outline was SiC. We have a significant increase over silicon solution inside the energy gap and the electric field. Now these two categories are what are enabling higher voltage operation. So we see SiC devices actually start voltage handling at about 1 kilovolt up to even higher than that with 1,200 volt devices available in the market today. This is a significant improvement over traditional silicon devices and enables us to have higher voltage topologies without needing to really go to multi-level technologies inside our inverter designs.
In addition, SiC has great thermal and melting point characteristics compared to even gallium nitride in this. This means that we can have very high junction temperatures inside the application. So they can handle much higher power loads without failing. This is great for industrial applications where we're trying to push a lot of power inside small packages. And it lets us increase the thermal density of the actual design as well, reducing overall system size.
And lastly, probably what's the most intriguing part about silicon carbide and gallium nitride is this electron velocity. Now it's a significant improvement over silicon because it enables extremely high switching frequencies. So DV/DTs that are very high like this allow us to switch faster without having to worry about switching losses like we would inside silicon. So we can get from one conduction state to another as fast as possible.
Now what all this means is that we can take the intrinsic properties of the high junction temperature and high electron mobility, and that in turn comes down to a lower recovering time during switching. So this means lower loss, higher switching frequencies inside our power modules. So less energy to dissipate.
Now on the total system solution, when we integrate that high junction temperature, the cooling solution is a lot smaller. The higher switching frequency means that we have smaller filters and passives, as we'll see later in the talk, as we start designing some of these actual filters. And that comes down to a total system size and weight reduction. So a significant improvement inside energy density.
And when we take a closer look at the silicon carbide system benefits, let's have a little bit of an example here. So in the top row, we can start looking at silicon carbon based inverters. So when you look at the chart in the middle, the three dashed lines are actually traditional silicon implementations. So as you can see, inside an inverter application, as we start increasing the switching frequency, the actual efficiency is going to be dropping fairly drastically, which is not something we see with the silicon carbide.
Like I said, we're going to be switching faster, which means that we have lower switching losses. And we can get to a full conduction state faster. And so as we increase switching frequency, we see a minimal drop-off inside system efficiency. This lets us get the switching frequency up to even 50 kilohertz or above. So it's an order of magnitude in some cases larger than some of the traditional system switching frequencies.
So when we look on the far right here, the actual total system breakdown. We can start reducing the size of the heat sink, the inductors, and enclosures. And that in turn, while the power devices are slightly more expensive because of the newer technology, the total system implementation cost is still lower than it would be using silicon devices. And we can also see just as a size comparison of a 50 kilowatt silicon based inverter versus a 50 kilowatt SiC-based inverter. And it's fairly easy to see the actual size that manages every gain by going to this higher energy density.
On the bottom here, we can see another example using an on-board automotive DC/AC converter. You can see, again, a significant savings inside the actual size of the inverter itself using silicon, or silicon carbide over silicon, as well as we can see some of the current traces here. So that tail current can be quickly cut off because we can switch a lot faster. Because of that switching speed and that ability to actually go on and off as fast as possible, we have higher switching frequencies and lower switching losses inside the system itself.
We're going to take a little bit of a look at where we're starting to see silicon carbide be used in actual applications. So across the gamut here for industrial applications. So we can start seeing on the low end of the voltage spectrum, power supplies in the 600 volt range that aren't really taking into consideration the ability for higher voltage, but they don't really need them there. So they're just going for the higher energy density that we can get from these higher switching speeds.
But as we start increasing device voltage, we can start seeing that as we approach over 600 volts into the 1 kilovolt range and above, when you start seeing great applications for EV charging for solar inverters, like we were talking about today, traction inverters, high power motor drives, and even into wind grid tie inversion and ships and vessels, where we're looking at multi megawatt single stage power conversion.
So silicon carbide is not just in the research and development phase. It's actually being implemented already. So there are several applications where we're already starting to see traction insight with silicon carbide in the industry. So traction inverters for rail, multi megawatt inverters where they're trying to get these down to be smaller, more compact and energy dense with less thermal output, powertrain inverters for EVs and HEVs, and then of course the EV/HEV on-board and off-board chargers. As the voltages for EV start to increase with larger battery packs, we see the benefits of SiC become immediately apparent.
So even with all of these benefits of using silicon carbide inside your design, there are still some challenges that we need to address before it really becomes available for mass adoption. So first off, we know that based on all the calculations and design work, that we can see the weight reduction in smaller size that's immediately apparent from using SiC. However, this is gained by getting our switching speeds up to 4 to even 10 times higher compared to what we've seen with IGBTs. So the challenge here is how do we reduce the switching losses whenever we're going to these higher frequencies? This is a topic we'll talk a little bit about later when we look at actually switching and driving the silicon carbide FETs.
Next up, there's a significant difference with these higher switching speeds when it comes to actually protecting the device itself. So the silicon MOSFETs, silicon carbide MOSFETs, actually have a reduced short circuit capability compared to their counterparts in IGBTs. So we're looking at about a 3 microsecond window where you have to be able to recover from a short circuit, versus about 10 for an IGBT. So being able to implement that kind of protection is critical to protecting these industrial devices.
In addition to the high DV/DT slew rates, it means that we're going to need higher isolation levels and CMTI levels compared to traditional component installations. And again, with the higher switching frequencies you need to be looking at how to reduce ringing and EMI. And so this high DV/DT can lead to highly increased EMI if it's not mitigated inside the design itself.
And finally, the system robustness is going to be critical to determine how long these systems can be out in the marketplace. And so with this high DV/DT, the higher component derating is going to lead to high system cost. So how do we handle high DV/DT without reducing system cost? And finally, looking at MOSFET lifetime. So reducing the ringing which could normally relate to damaging the actual MOSFETs themselves.
So if we look at this, the primary considerations we need to look at is ringing and EMI, and then taking care of that short circuit capabilities. And also, adding in the higher isolation. So taking care of these few things can lead to significant challenge solutions for a silicon carbide system.
So now that we've taken a look a little bit at what silicon carbide is and what it can do for us, and some of the problems we'll have to address, let's take a little bit of a look at the topology and FETs that we'll be using inside this particular inverter design. As I mentioned in the introduction, this is going to be a multilevel inverter with some new topologies to TI. And so we'd like to cover a little bit of that and some of the advantages that we can see by using a different style of inverter topology compared to what we have done traditionally.
So what I'm showing here is just a traditional polyphase H-bridge inverter. So we can see for a three phase inverter, we have six switching FETs. And it's fairly well understood. So this is a normal kind of low voltage application for IGBTs inside an inverter topology. The commutation is very straightforward. So we can see that DC+ can easily commutate through Q1 into the R branch. And the DC- can commutate through Q2. Fairly straightforward. Since the control system is fairly well understood, a lot of optimization has been done for this particular type of design. But we can see that there are some limitations to this implementation. So in order to get higher voltages, Q1 and Q2 will both need to be incredibly high voltage devices. So we're starting to already see the limits of what can be done with IGBTs in this space, as they're topping out at about 1,000 volts of operating capability. So that would severely limit the voltages on the DC bus.
In addition, the neutral is just clamped between two capacitors. So it's kind of referenced via those caps. And so we're depending on some passive components here in order to properly center our neutral voltage between DC+ and DC-, which can potentially lead to some balancing inside those caps, which would let neutral float away. Now there are obviously solutions to mitigate that. But from a simple standpoint, it can become a problem.
So the topology that TI is proposing is called a T-type inverter. So this is a neutral point clamped version of the standard H-bridge. So we can see that we still have Q1 and Q2 in the standard H-bridge configuration, but we've added Q3 and Q4, which will clamp that center point to neutral.
Now for this implementation, in Q1 and Q2, those will be silicon carbide devices. Those need to be able to withstand the full DC bus voltage just like in the traditional H-type inverter. But if we use silicon carbide here, we can take advantage of the high voltage handling. And so these can be 1,200 volt devices without much worry.
Looking at Q3 and Q4, since they're stacked back to back like this, it means they only have to handle half of RD ceiling voltage. So these can actually just be 600 volt devices. This means that it's just a simple extension of a two level inverter by adding in these additional six switching components.
So these bidirectional legs, we see they're in a common emitter configuration. So the emitter gate voltage is reference to the same point on this particular design, which means that you only need one additional gate drive bias supply in order to operate the T-leg. So from this additional component standpoint, we only see the extra two switches, two gate drivers, and a bias supply in order to effectively create this configuration.
As we can also see, what this does is it lets us clamp to neutral whenever we are in an off state. And so that lets our neutral actually be referenced exactly to the center of those bias caps so that we don't have to worry about a floating neutral, and we can get a more stable voltage output.
So what we can see from an advantage standpoint, we have a few things that are carried over from the H-bridge. So we maintained low conduction loss. This is because we have only a single switching device inside our conduction path as we go from, say, DC+ to the output. There's still a relatively small part count compared to other neutral point clamp topologies.
And as we'll see a little bit more later, the switching operation is actually fairly straightforward. However, we do have a few upgrades to the H-bridge configuration, which include lower switching losses, because we do have that ability to clamp to neutral. And then we also have lower output harmonics because of that. And because of the lower output harmonics and using silicon carbide and switching faster, we can see a significant reduction in the actual filter size that's implemented in the inverter itself.
So lets take a quick look at the two of them side by side, and look at some of the efficiency comparisons that we can make between the traditional two-level full bridge and the three-level T-type. So for these efficiency calculations, what we have gone and looked at is a three phase, 400 volt output for 10 kilowatts of output power, a DC input of 800 volts, and then our inverter switching at 50 kilohertz with about a 20% current ripple taken into account in the filter.
For the two-level bridge, we see our MOSFET losses, even when using silicon carbide, are about 9.4 watts per FET. And our inductor loss is almost 9 watts. And these are also-- we look here. Because of the design of the system, these inductors are going to be 833 microhenry.
When we move into the T-type, because of the reduced output harmonics, we can already see a benefit with our inductor sizing. So our inductors are now in the 500 microhenry range. So we can start to see significant reduction inside the inductor loss. So here, it's only 6.4 watts. In addition, we can start seeing some of the benefits of this system with the losses in the silicon carbide FETs dropping significantly from 9.4 down to about 5 watts. And then we only have the addition of the IGBT, or silicon MOSFET losses here.
So in the center chart, we can see an arrangement where Q3 and Q4 are IGBTs. And we're seeing about 8 watts of loss in our estimations. And then finally, using MOSFETs for that center leg. And then the total losses for MOSFETs is only about 2 and 3/4 watts.
What this means is that our total loss inside a two-level full bridge using silicon carbide at 50 kilohertz comes to about 83 watts, which would be about 99.1% efficient. Using IGBTs, because of the IGBT losses, you can see a slightly increased total loss of valuation. So our efficiency drops to about 99%. However, if we use silicon MOSFETs, we can see that the total efficiency is well above 99% because our total system loss is only about 70 watts.
So next up, let's take a little bit of a closer look at what's driving these particular last values for each of these particular configurations. So let's first take a look at the loss details of two-level silicon carbide inverter. So what we've done here is we've broken this into switch speeds of 20, 50, and 100 kilohertz. Right off the bat, we can see that the inductor value drops significantly as we increase switch speed, as expected. But every time we double the switching speed, we can see approximately reduction in half of the inductor value required for that particular inverter.
We can also start to see what's driving some of the losses inside this system. So as we start increasing our switch speeds, as expected, the silicon carbide switch losses are going to start increasing, because we'll spend more time inside our switching state by comparison to our conduction state. And there will become a time where the two of these cross. And it's not as feasible to run inside this state. So the switching losses will start to dominate after a short time. We see, though, it matches up the 50 kilohertz switch speed this. It's a loss of about 83 watts for the system.
And now we can start to get to some of the more interesting results when we start looking at the three-level silicon carbide plus MOSFET configurations. So once again, we've broken this into 20, 50, and 100 kilohertz. And we can already see because of the multi-level configuration, the inductor values are already significant reduced, even at the higher levels and lower levels of our switch speeds, compared to the two level configuration.
So even just moving to a standard T-type topology would result in inductor value loss because of the output harmonic reduction. And so when we start looking at the loss graph here, as we start increasing switch speeds, the silicon carbide conduction losses drop fairly drastically. However, they're offset by the losses we're going to start seeing inside the inductor. MOSFETs do a great job at being able to switch faster compared to IGBTs. So we don't see much loss increase on those whenever they start going up in switch speeds.
However, you can see, though, that the silicon carbide conduction and switch losses are not as drastically changing as they were before. This is because of the conduction path that we have available to us inside the T-type. We can start reducing some of these conduction losses that we saw using just a single layer.
So if we take a look at the same configuration but using IGBTs, we can see a few things that are the same, but a few that have changed on here. So mainly, what we can start seeing is the IGBT switching losses start going fairly high whenever we get into the 100 kilohertz range. So at that point, this IGBT was going to be our primary driver of losses as it increases like this. But it is fairly linear across the range of switching frequencies.
Now, I've highlighted here the 50 kilohertz IGBT configuration, because that's the one we actually went with inside this particular inverter design, as we'll elaborate more on later. It might not look like the best choice at this point. However, there are some trade-offs that we do have to consider. The system efficiency is not the only thing that we care about whenever we're designing one of these inverters.
So whenever we look at IGBTs and why we chose them over the silicon MOSFETs, there's two main reasons. So the silicon MOSFETs have a resistive feature, which helps reduce conduction loss at light load. And this is why the efficiency is so much higher on them. However, they have a reverse recovery body diode, which increases voltage and current overshoot. Since they switch so much faster, the recovery is actually a lot more severe when compared to IGBTs.
The silicon IGBTs have a higher conduction loss at light load. But the reverse recovery can be managed a lot more easily. In addition, we can also add an external antiparallel diode from silicon carbide, which would even more reduce that recovery losses. Since the IGBT is unidirectional, current will always conduct through one of the antiparallel diodes in the T-type topology. And the light load efficiency will be reduced.
However, when it comes down to it for this particular design, we found that the silicon carbide MOSFETs just switched so much faster. The MOSFET body diode had so much higher losses and overshoot that it was unfeasible to find a MOSFET of high enough voltage rating to handle this overshoot. So for that, we had to switch to the IGBTs. So in a lower voltage system, the silicon MOSFET could still be a useful device for this. However, going to 1,000 volts, The IGBT just won out because it had the higher voltage handling capabilities and the better reverse recovery capabilities.
So far in this presentation, I've alluded to a few things that increase the efficiency and other benefits of this T-type topology of an inverter. But we did see earlier that the conduction and the commutation is going to be a little bit more tricky compared to the traditional H-bridge inverter. So I'd like to take a little bit of a deep dive on that and really start to look and understand it, what it takes to drive one of these inverters, and show that it really isn't as complicated as it looks from the get-go.
So first off, let's look at a traditional schema of an H-bridge and the conduction path that would need to be taken. So in particular, this is a single phase of a classic H-bridge style three-phase inverter. So we're just looking at a half bridge rather than the full H-bridge is that we would have in a single phase device to make things a little bit easier for us here.
So if we look on the left-hand side, that's our generic schematic here with Q1 and Q2. It doesn't really matter in this particular case what those devices are specifically made of. However, we can see since there's only two devices, we only really have four different conduction states. So in the top left of the right hand diagram, we see both off. In this case, there's nothing conducting.
When we go to the top right, we see that Q1 is turned on, which enables conduction from DC+ out to the branch. This is voltage just conducting out. And then this would also have a return current coming in from neutral and being referenced to that neutral leg. In a three-phase system, however, that neutral is just a voltage reference and isn't really a current conduction path. In the bottom left-hand state, we can see Q1 and Q2 switch, which means that we're now commutating DC- minus to R for the negative half of our voltage sine wave. And similarly, neutral is just being used as a reference point.
And then in the bottom right-hand side, we do see a state where the Q1 and Q2 are both on. This would result in a short circuit. And it's technically an invalid state, and should be protected inside the inverter itself. So on a simple, three-phase inverter for a single leg, there's only these four different states. And it's fairly easy to manage and apply a PWM to either Q1 or Q2 while keeping the other one on or off in order to generate that sine wave.
And speaking of the PWMs, we can see it's a fairly straightforward commutation for this. For the positive half of the wave, Q2 is kept off while Q1 commutates on and off in order to generate the sine wave. And for the negative half of the wave, Q1 is kept off while Q2 gets a PWM duty cycle in relation to what part of the sine wave it is. Again, simply two signals and a fairly straightforward commutation example.
So let's look a little bit closer at the T-type commutation. So we have two different states that we really need to consider here. For this particular example, we're going to ignore the negative half, because it's really just the positive half in reverse. So for these two states, it's the positive half of our sine wave. And so we're going to look at commutating from DC+ into R, and then from R to DC+ for the reverse action.
So whenever we start out, we can look on the left-hand diagram here. Part A, we have Q1 on, Q3 on, and Q4 off, and Q2 off. In this case, we have current conducting from DC+ out the R branch through Q1. We can see this conduction path only includes one device. So we only have to worry about the losses across Q1 whenever we're positively conducting power out DC+ to R. And this is very similar to what we saw in the h-bridge topology in the previous slide.
Now to start commutating back to neutral for that reference point, the first thing we do is turn off Q1. What this means is that since Q3 is on and Q4 is off, though, we are going to conduct through the body diode of Q4. So Q3 stays on and enables this. And then we have a neutral point clamp for R out through Q4.
And by design, this is a safe commutation path for the power to come out. So if Q1 turns off, it will automatically reference down to neutral. And then to continue to secure that clamping in part C here, we turn Q4 on. Now the opposite case is whenever we need to go from neutral back to DC+ as our reference. And so we can start out here with Q3 and Q4 on and Q1 and Q2 off.
Now to start the commutation back the other direction, it just operates in reverse. So Q4 is turned off. And then Q1 is turned on. When Q1 is turned on, the current will naturally conduct from DC+ to R again. So rather than just turning one FET on and off, we do have to run them in this specific sequence in order to ensure that we have the neutral point clamping working effectively. However, keep in mind that this additional complexity does let us reference a lot more accurately to the neutral force between DC+ and DC-, and have a much more balanced output with lower output harmonics.
And so if we look a little bit closer at this, what this actually means is that part B for both of these is what's going to be called a deadtime. And so this is going to be the time delay between switching Q1 off and Q4 on, or vise versa, as we'll describe a little bit closer when we look at the specific PWM charts in the next slide.
So if we take a close look at the actual topology here, what we've essentially established is that Q1 and Q4 are operating as a pair of FETs. And then Q3 and Q2 are just in a static configuration depending on what stage, if we're in the positive or negative half. So when we actually look at the PWM output of our controller for this specific application, all we have to do is drive Q1 and Q4 in a complimentary fashion. And whenever we go into the negative half, make sure Q1 is off and Q4 is on while Q2 and Q3 then have their complimentary cycle.
Looking a little bit closer, we can zoom in on this PWM graph. And we can see where that deadtime occurs. So Q1 will actually be on slightly less time, depending on how it is. And that's that deadtime zone that we talked about while we're switching the commutation cycle between the DC+ to the neutral.
And so you can see here that even though we're adding those additional two switching devices, it's actually a fairly straightforward commutation example. And there isn't a lot more complexity that we need to worry about. These are actually all fairly straightforward to set up with most modern DSPs in order to have this pair of FETs operating with each other with that deadtime integrated.
So we've looked a little bit at some of the benefits of using silicon carbide already, what we get out of using a T-type, and some of the commutation examples. But we need to look a little bit closer at what it takes to actually drive a silicon carbide switching device. As we talked about a little bit earlier, there are some drawbacks to using silicon carbide in these very high DV/DT scenarios. And we need to see how we can start mitigating that using a gate drive topology that works effectively for silicon carbide.
So first off, we need to ask the question, what is a gate driver? And so in general, it's a power amplifier that turns a low power signal from a controller IC into the high current gate drive for a power MOSFET. Now, MOSFETs don't work just on voltage alone. They do need a current drive, because there's a charge that's required to drive that gate in order to effectively get the switching device to go into saturation or not.
So in most of these cases, our digital controller will have a low voltage, low power output. And so we're just using an amplifier here, typically an H-bridge configuration, in order to drive the high current output requirements for our FETs themselves. In this particular case on the top left-hand side, we can see that low voltage input. And we can also add higher bias voltages for this as well. Different FETs will require different voltages for switching on and off, and different current levels depending on the charge required to turn the switch on or off, as well as how quickly we need that to switch. And so that can be configured using R1 in this example.
So in most cases, we can see here that whenever we're driving through this H-bridge, it's a simple case of driving a positive voltage into our amplifier, which will then go through into our gate itself as a current waveform. In order to get the gate drive to drive completely off, however, oftentimes we need to actually go to a negative voltage compared to our gate source voltage. And what this does is it allows us to ensure that the gate is fully off and avoid any kind of Miller trips, which would be any kind of stray voltages causing the gate voltage to rise above its threshold level. And so we need a system that can effectively drive the gate both on and off in order to make sure that it has a stable operation.
Now an additional consideration on the benefits of using a gate driver is that we can actually output a lot more current. And so this lets us quickly charge or discharge that gates capacitance. What this lets us do is quickly switch and reduce our switching losses. We talked about it a lot earlier. Because of silicon carbides faster switching losses, we're going to need to look at gate drivers that have an output capability able to drive them fast enough in order to take advantage of that.
Now lastly, we do have a few different configurations of gate drivers to consider. So first off, the easiest one is a low side driver. And so this is one where the gate is referenced to the ground of Q1 on this particular design. Everything referenced to ground makes it a little bit easier to design and control.
However, in most cases, we're not going to be that lucky, and we'll need a high side, or even an isolated gate driver so high side drivers can typically go up to 80 to 100 volts. And so even inside this application, a high side driver will not have the ability to withstand the kind of voltages we're looking at. But in essence, what it means is that the gate doesn't need to be referenced via its emitter to ground. And so we can also do a similar application with the high side drivers using full digital isolation, which we'll talk a little bit about later, and why we're going to need excellent isolation for a system like this.
So we've talked a little bit about this before with the challenges of driving our silicon carbide FETs. But let's look at the most critical requirements that we're going to need to look for in a SiC driver. And so first off, when we're talking about voltages of 1,000 to 1,200 volts, we're going to need isolation. A simple high side driver will not be enough in order to protect these devices with that level of switching voltage.
Now again, I mentioned before a high DV/DT immunity, or CMTI, is going to be critical based on how quickly we are going to be switching these devices. Another problem that we mentioned earlier is because of some of the issues we have with silicon carbide and its ability to withstand short circuits, we're going to need very quick overcurrent and short circuit protection for these devices. And that should be built into the gate driver itself so it can quickly shut the gate off if there's an error.
A low propagation delay and variation across that isolation barrier is critical whenever we're doing high speed controls and applications in order to ensure efficiency. We really don't need these devices stepping over each other and going into short circuit for even a few microseconds, because that would really reduce a lot of the efficiency gains that we're going to be getting here. And finally, silicon carbide really appreciates a high output drive voltage. So we need to look at gate drivers that are able to provide this kind of drive voltage to effectively turn them on and off.
So let's take a little bit of a closer look at some of these key requirements. So first off is a high output drive voltage. Most silicon carbide FETs need a drive voltage of about 25 to 35 volts. Like IGBTs, silicon carbide has a thick gate-oxide voltage. They are typically driven around 20 volts, but are able to be overdriven fairly easily. What this does is it ensures stable operation inside noisy environments.
We also need to consider the negative supply voltage and so what that means is that we would actually prefer to drive the gate off to a negative voltage. And this reduces Miller turn on issues. So that means is that whenever there's a noisy environment, stray voltages and EMI on the line will not accidentally turn our silicon carbide FETs on whenever we would like to be driving them off. So driving them to zero is actually not as acceptable as driving them to a negative voltage.
Most silicon carbide FETs actually do start to turn on around 3 to 5 volts. This is fairly critical inside their operation. And even a small transient could cause system breakdown and lead to false turn on conditions. So in addition to effectively turning these on and off, a high overdrive actually reduces the switch resistance so we can start putting it into that saturation region while it's on. And this is going to reduce our conduction losses. However, the gate oxide can break down fairly quickly, so we need to be careful to not overdrive them too much. So there is a balancing point here with the drive voltage.
So again, we're going to need a higher drive strength, as well, in order to get this higher efficiency, lower switching losses. We do switch faster than IGBTs using silicon carbide, but require higher currents. This higher switch speed leads to higher DV/DT. And so what that means is that we're also going to need high CMTI.
But what we get out of this high drive strength is that we get to spend less time inside our switching region. So if we look at the charts here, we have our drive strength peak on the list here. And when we have a low system, we have VGS, and VDS, and ID shown. So with ID using a low drive strength, we see the slope of the DI/DT phase being fairly low.
So our switching loss is actually determined by the area under both VDS and ID. So we can see in this case that the low slopes of VDS and ID lead to a fairly high switch loss. By being able to drive much higher strength, we can significantly reduce the area under both of those curves and reduce our switching loss.
This high switching costs avoidance, though, means that we need to worry about high CMTI. And so since we're looking at about 100 volts per nanosecond inside this high speed switch, the high CMTI is going to be a strong requirement for system robustness and higher efficiency. We're going to have a little bit more on the isolation technologies and what drives CMTI a little bit later.
The next thing that we need to look at is really fast short circuit protection. We talked about earlier, we need short circuit protection, typically sub 2 to 3 microseconds in order to effectively handle silicon carbide devices. And this is for a variety of reasons, mainly that the disulfur silicon carbide is significantly smaller. So it has a lot less thermal dissipation, which leads to lower current handling. And so that's where this 2 microseconds comes from, that the silicon carbide FET just can't handle the same amount of surge protection.
So the normal system that we use to detect for short circuits inside a FET is going to use what we call desat. So what desat detection does, typically, is it looks for when an IGBT is going to exit the saturation region. So if we look at the drive curve for an IGBT of VCE versus IC, we can see that in normal operation, we are in the saturation region.
And so on an IGBT, they normally operate in the saturation regions. But when a short circuit happens, the collector current increases drastically, and so will VCE, and it usually plateaus off. And that point, the IGBT is entering the active region, which is easily detectable by VCE. So a circuit that can detect VCE effectively will effectively determine when we are in the active region and be able to shut the IGBT down. Since the IGBT can handle the extra surge current, the typical 10 microseconds of a desat detection circuit is normally sufficient.
Silicon carbide MOSFETs, on the other hand, operate in the linear region. So the collector current will not be self-regulating like it is in the IGBT. The silicon carbide FETs act a little bit more like a resistor in this way. As VDS goes up, so does ID in a reasonably linear fashion.
So during a short circuit operation, the silicon carbide FET should enter saturation, as shown here on the chart. However, this transition happens at a much higher VDS. And since it's not self-limiting, the transition may actually never happen before the silicon carbide FET fails. So we need to make sure to detect that VDS increase quickly and shut the device down, because it could never start to self limit.
So additionally, we also need to be looking at faster switching speeds and lower propagation delay in order to get tighter system control as we start increasing our switch speeds. So these can be enabled with a shorter propagation delay. This also lets us reduce deadtime and increase efficiency of our system. And finally, actually temperature switching of the switch can help with advanced protection systems. So in addition to our desat short circuit protection, being able to sense the temperature of the silicon carbide FET itself and make sure that we maintain operation inside a safe region.
As we mentioned earlier, one of the critical functions of a silicon carbide based gate driver is the ability to detect short circuits and prevent them. In order to evaluate this in TI's own ISO5852S gate driver SiC-based switches, we have developed an evaluation board for testing both double pulse as well as short circuit detection and prevention. This hardware contains everything required to run the isolated gate drivers, including isolated power supplies with DC inputs and a DC bus in order to simulate a traditional converter, and an inductor as well, in order to perform the double pulse test and check all the timings. This particular piece of hardware lets us test reliable operation up to plus or minus 15 amps and perform all these tests on the SiC modules themselves.
So lets take a little bit of a closer look at some of the test results that we've seen from these drivers and show that we can reliably detect and prevent short circuits and safely stop the six switches in time to prevent any damage, as well as reduce EMI through them. So the first test we're going to look at here is a delayed load short into a SiC device. As we can see here on the left, this is with a standard hard turn-off procedure into the SiC FET once it reaches a desat limit.
So we can see here that ID overcurrent is about 1,000 amps. And we're seeing ringing up to 400 volts. This creates some pretty significant EMI using the hard switch methodology here. On the ISO5852S, in order to prevent this kind of overshoot, there's actually an implemented soft turn-off feature that will slowly reduce the gate drive strength and bring down the SiC switch a lot more gracefully. As we can see on the right, by enabling this soft turn-off functionality alongside the dsat protection that we have for the SiC FET, once that desat pin does reach the threshold that's set for it, we can see that the V-gate will slowly drop off, gently reducing the SiC FET out of its [INAUDIBLE].
In this case, the ID current was over 2000 amps, but it was gracefully brought down. And we can see more critically the VDS overshoot is limited to less than 50 volts, compared to the 400 volts of ringing that we saw in the left-hand case here. We can also see, based on the timings here, that we have a short circuit protection less than 1 microsecond, which is sufficient for SiC devices to prevent device damage. So with this particular device, the ISO5852S, we have a very fast short circuit protection, as well as a VDS overshoot limit using the soft turn-off functionality. And this results in functionality of safe and effective shut-off and shutdown procedures for the SiC FETs.
For this next test, let's look at sick devices being turned on into a short circuit condition. If we look again at the left, we see a very similar chart where we have the V-gate being driven high as a SiC FET goes into short circuit condition. The ID overcurrent over 1,000 amps coming from those DC bus caps. And during the hard shut-off case, we see VDS again overshooting and ringing above 400 volts.
If we look, though, at the right-hand side with the soft turn-off functionality, we have the V-gate driving high. As the device starts to enter saturation mode, we see the desat panel hit its threshold. It will be rapidly detected and then gently brought down to prevent damage to the FET and prevent ringing.
So we can see the VDS is, again, limited to about 50 volts. So that VDS overshoot is basically null and void in this case. And we have effectively protected the SiC FETs from a short circuit condition and safely brought them into an operating range.
For a little bit of an overview on the device used in those tests, look here at the one page sheet for an ISO5852S. So this is an isolated, high CMTI gate driver with Miller clamp functionality. So it's using a full integrated silicon dioxide dielectric capacitor-based isolation feature. So this enables that high CMTI that we saw as a requirement earlier on. And we'll talk a little bit more about capacitive isolation in the next section.
In addition to that, this also integrates a lot of safety features that we require for these high voltage devices. So Miller clamping in order to ensure that the device is successfully brought low and kept low. We have the desat detection that we just previously talked about. Undervoltage lockout. Fault feedback. So there is actually a way to detect whenever there is a fault condition.
And there is also ready feedback as well as that auto soft shutdown on short circuit that we mentioned in the previous section, as well. In addition, this is a full reinforced isolation configuration. So it's capable of up to 12.8 kilovolt peak surge and a 5.7 kilovolt RMS isolation rating.
This device is also capable of the kind of speeds required for silicon carbide-based operation. So it has a very low propagation delay of 110 nanoseconds, as well as full ESD protection for these high voltage systems to prevent any kind of damage to the system that would create unsafe conditions. So for driving silicon carbide FETs effectively and safely, The ISO5852S is definitely the most recommended part in TI's current portfolio.
Since we've been talking about this T-type converter and using a mix of different switch topologies, it's also worth considering a driver for the IGBTs, or silicon-based MOSFETs, that are on the T-branch in this particular design. So for the design that we'll be talking about in a moment, we recommend and use the UCC5320 device. This is another isolated gate driver, but it's a much simpler configuration than the one used for the SiC FETs. In this design, it's unlikely that you would see the kind of short circuits through neutral on that T-leg, because they'll be prevented via the actual H-bridge itself being shut down so that the power won't be able to short into that mutual leg. So a much simpler way driver is available here for use to reduce system complexity.
So the UCC5320 has an integrated silicon dioxide dielectric isolation, again. So we do have full isolation here. This particular one is both available in basic and reinforced packages, depending on the system safety requirements, and operates just like a traditional gate driver for IGBT.
Since IGBTs are a fairly known quantity, the particular configuration available for the device is selectable by the customer based on the actual features that they need. So we have somewhat different UVLO options and different ground references available, all with similar drive characteristics and low propagation delay, and high CMTI that we looked at inside the previous device. So for driving the simpler IGBTs and MOSFETs, it's worth considering an effective gate driver. And our UCC5320 family is highly recommended.
One of the other key functionalities that we've talked about already is isolation in high CMTI for these high voltage inverter systems. We haven't talked much about grounding, but we'll cover that a little bit and see where isolation has a play, and what requirements we have, specifically around the isolation technology, in order to ensure an effective and safe system.
So let's take a little bit of a look at some of the compliance standards required to monitor leakage currents inside the systems as it relates to system grounding. So the primary one that we're going to look at is the German standard VDE 0126-1-1, where we have three different fault currents that need to be monitored. First off is the ground fault current, which is in case of an insulation failure when the current flows through the ground wire. Secondly is a fault current, which is the sum of the instantaneous values of the main currents that would normally be zero.
And then lastly, we have leakage ground currents. And this is due to stray capacitance via the insulation and cabling where parasitic elements couples the grounding into and through that insulative barrier. So the standard states that disconnection in any three of these particular leakage current issues needs to happen within 0.3 seconds whenever that leakage current is higher than 300 milliamps.
This means that we need to actually take a close look at how we provide system grounding for the entire solution. So on the left-hand side here, we have a human accessible control module, as you can see in the bottom of the diagram. Since that control module is grounded to earth and the actual-- not the DC bus itself. Everything that we're doing with sensing and gate driving does need to be isolated. So we can see that the low power side of the gate drivers and all of the sensing is earth grounded.
So these isolated gate drivers and amplifiers are referenced to the same ground as the control module, which means that that control module side is safe for human interaction. And these also require safety isolation. This is a simpler configuration compared what we have on the right-hand side, but it does require a higher isolation standoff. On the right-hand side as an alternative methodology of integrating the system where the control module is actually referenced to DC-.
This introduces additional isolation requirements on communication interfaces because the control module is not human accessible. It's more complicated, but there is a lower isolation requirement on the actual isolated elements inside the system itself. However, again, all of the communications will have some kind of digital isolator requirement. Because of the simplicity of that solution on the left, this is the one we've decided to go forward with on the actual design of the inverter that we'll be talking about later.
As we start talking about the different levels of isolation, let's look at some of the major technologies that are available in the market space to maintain this kind of high level of isolation that we require for both sensing and driving. First off, probably one of the oldest methodologies of isolating an electrical signal is via optical isolation. So inside a single package, there will be an LED and receiver. So the LCD side will generate a pulse of light that will be received by the diode on the right-hand side and create an output. That has a signal conditioning and LED drive circuit requirement. So this is a current-controlled solution.
And then on the right-hand side, there is a CMOS buffer that will interpret that signal and drive an output. In the middle, we have a magnetically coupled isolation technology. So that would be a driver on the left that will then drive through a magnetically coupled transformer-based system. And then that signal will be interpreted on the right-hand side. And then finally, the third option, and TI's primary methodology of isolation, is capacitive. In this particular one, there is an amplifier with an offset that will generate an electric field via capacitive element. And that signal be interpreted and driven out via an output.
So let's take a look at some of the drawbacks of both optical and magnetic isolation that lead us to see why TI prefers capacitive-based isolation solutions. So first off with optical isolation, these are fairly low performance devices. They suffer from long propagation delays high quiescent current because of the requirements to drive the LED. They also have a low robustness and reliability. So they have a low noise community because of the common mode transient immunity is low. And the LED will degrade over time and temperature, which leads to reduced lifespans.
On the magnetic isolation front, they suffer from a low robustness issue. They have lower working voltages, which translates to limited applications. They have a low noise immunity because they are using a magnetic coupling. So any kind of magnetic interference can cause a problem for that magnetic coupling. And they have high EM emissions because they are generating their own magnetic fields internally. They also suffer from a low reliability with high quiescent current, and an insulator degradation over time.
Capacitive isolation, on the other hand, doesn't suffer from any of these drawbacks. So let's take a close look at TI's capacitive signal isolation. So this is the industry leading integrated capacitive isolation. Silicon dioxide is the most stable dielectric over temperature and moisture, which leads to very long lifespans. We can leverage advances in TI's CMOS process for high precision, type part-to-part skew tolerances, no mechanisms to wear out, a low defect level. What this means is the highest lifetime in the industry, greater than 1.5 kilovolts RMS for over 40 years, and superior transient protection in harsh environments, such as solar inverters.
You can see some of the test results from the actual devices themselves. This one in particular is the u.s.s. UCC21520 being tested with CMTI. So we can see on the left hand chart a positive CMTI of 155 volts per nanosecond. And while we have OUT A and OUT B are both relatively stable with only a minor amount of noise being coupled in. You can also see a negative CMTI of about 200 volts per nanosecond with, again, similar output stability. The high CMTI immunity that we're seeing here inside the UCC21520 translates to excellent performance inside high switch speed applications, such as silicon carbide-based inverters, especially with the higher voltages that we're starting to see and operate with.
So for the actual implementation of this three-level silicon carbide based inverter, what we're going to be showing is TIDA-01606, a 10 kilowatt silicon carbide-based T-type inverter. So let's take a little bit of a closer look at some of the system design methodologies and topologies that were used for this particular TI design.
So first off, let's look at some of the key design specifications for this particular TI design. Primarily, we're looking at a 10 kilowatt inverter. We are expecting a power factor that is adjustable from 0.7 lag to 0.7 lead in order to compensate for non-unity power factor on the grid. We're looking for grid level voltages of the 400 volt line to line, plus or minus 20% on this particular one. So that is adjustable based on the controls there.
There's a three-phase design that operates at both 50 and 60 Hertz, with a maximum current of 18 amps. The DC input is a nominal rating of 800 volts, but it can go from 600 to 1,000. By adjusting the PWM of the output, we can maintain a stable AC output across this entire range of DC in. Our target efficiency, as we mentioned earlier, based on some of the equations, and--
So lets look at some of the key specifications when we're taking into consideration when designing this particular TI design. First off, we're looking at a 10 kilowatt base design with a power factor of 0.7 lag to 0.7 lead, which is adjustable to let that inverter help compensate the grid for non-unity power factors. This is operating in a grid voltage of 400 volts and three phases at 50 to 60 hertz and a maximum current of 18 amps. The DC input is nominally 800 volts, but because we do have the control system in place, the input can range from 600 to 1,000. And that 1,000 volt rating is enabled by the silicon carbide-based devices used inside the system.
Based on the efficiency calculations we did previously, we are targeting an efficiency of 98.5%. And also with the filter design, a target output THD of less than 2%. In addition, this will be a grid connected inverter. So it will use the grid sinusoid in order to generate its own output in an operating temperature of negative 25 to 60 degrees C with forced air cooling as a thermal management target.
So lets take a close look at the topology and system architecture of this particular TI design. We can see the standard three-level T-type inverter that we discussed earlier. On this one, we're using silicon MOSFETs for our primary H-bridges for all three phases, and then silicon IGBTs for the neutral point clamps on the T-leg. The output of the actual switching section is measured by hall sensors into an LCL filter, which will filter out the harmonics. And then the voltage of the LCL filter is measured in order for voltage feedback into the system itself.
The output current is measured via three isolated shunts. And then the actual grid level voltage is measured on the other side of an output relay. So this enables us to detect the grid voltage, synchronize to it before actually closing the relays to ensure safe operation.
The actual inverter currents are measured via an OPA4340. We're measuring all of the voltages across the system using dropper resistors into an OPA4350. And then the actual shunt resistors are being measured via the isolated AMC1306. So all three phases have isolated current measurement on the output. All of these signals feed into the heart of the system, the F28377D control card, which is using a Delfino class C2000 processor to run all of our control logarithms.
The system has a power tree in order to power all of the bias voltages across a system using a nominal 15 to 60 volt input. And we'll talk a little bit more about the actual power topology in a moment. For each of the phases, we have a dedicated driver card, which will have an ISO5852, one for each silicon IGBT, and then two UCC5320s to drive the IGBTs. Each of these control cards also contains a UCC27211 to generate all of the bias voltages. It also has buffers and reset circuitry in order to protect the actual gate drivers themselves and ensure continuous drive. And these are connected to the 28377 control card so we can monitor any fault conditions, apply resets, and also send all of the PWM signals required out to the system.
Here's a closer look at the power tree inside TIDA-01606. So first off, we have that 15 to 60 volt input with a 12 volt output via the LM76003 switch mode regulator. So this 12 volt output will be sent to all of the gate drive cards to generate their own bias voltages. However, on the main board itself, we drop that 12 volts down to 5 volts using the PTH08080 integrated module. And then we have a TLV1117 LDO for the 5 volt to 3.3. And this will generate the 3.3 volts for all of the analog, as well as the control card circuitry.
Since we do have isolated current shunt measurements, we're using an SN6505B for each of those, which will generate an isolated 5 volt output for the high side of those isolated shunt measurement amplifiers. On the other side of that isolated measurement, we're bringing the 5 volts down to a stable 3.3 using a TLD70450. On the actual gate drivers themselves, that 12 volt input is driving a UCC27211, which will then be using two CSD88537ND FETs inside a half bridge.
Now, all of these will be driving three different transformers inside an open loop configuration because these transformers are specifically designed for the outputs to power the silicon carbide gate drivers at plus 20 and minus 5 volts. So we have two bias transformers for that. And as I mentioned earlier on, only one bias transformer is required for the silicon IGBTs, since they do have a common emitter. So that single transformer is set up for a plus 15 to minus 5 volt operation for the IGBTs.
So here's a closer look at that gate drive card that we'll be using to actually drive all of the FETs. We can see here, we have the two ISO5852S devices for the silicon carbide devices. And we have the two UCC5320s for the IGBTs. For the particular design, since we have four devices we're trying to drive from the PWM signals, we're using an SN74LVC126 buffer. What this will actually do is clean up a lot of the signals coming across the power board from the MCU in order to effectively drive all of the gate drivers.
This is a fairly common configuration. And we can also see the UCC27211 and the CSD88537 half bridge for driving all of the bias supplies. This particular design, again, we have the PWMs for all four channels coming in. We have a reset as well as a fault signal to report any kind of issues back to the controller itself so that the system can be effectively shut down and disconnected.
Let's take a closer look at some of the voltage and current sensing topologies used inside this design. So on the left we have our AC voltage measurement. So this is actually going to be one of the configurations for each phases. So we're measuring phase voltage by referencing it to neutral. And by using two dropper resistors into the OPA4350, we can effectively measure each phase's voltage without having to worry about high voltage operation into the OPA from phase to phase by dropping it down via these 5 megaohm resistor. The output of the OPA will then fed feed directly into the DSP of those ADCs.
On the right-hand side, we can see the AMC1306 being used for isolated measurements of those output shunts. So we have an SN6505 with a 5 volt input and that LDL and the other side in order to provide the isolated bias supply. What's a little bit different about this AMC1306 compared to the analog system on the left-hand side is that the output is actually a bitstream. So it's a digital out that will feed into inputs on the DSP itself. That DSP bitstream can then be filtered and decoded by the C2000 and convert it into analog measurements. This provides an effective, noise-immune measurement system for output current of the system.
We've already talked a few times inside this presentation how a faster switching speed enabled by silicon carbide devices is going to result in a reduced total system solution size of the inverter itself. This is because of the size of the output filter and the magnetics primarily inside it. What we can see in the top right here is a simple schematic of an output filter for a single phase of one of these inverters. So in this, we have an inverter side inductor, a grid side inductor, the capacitor, and then the resistor that goes alongside it. So this whole filter is used to attenuate any kind of switch noise onto the power line, give us a nice clean AC output, and also attenuate any kind of higher order harmonic.
We've already talked a few times inside this presentation how a faster switching speed enabled by silicon carbide devices is going to result in a reduced total system solution size of the inverter itself. This is because of the size of the output filter and the magnetics primarily inside it. What we can see on the top right here is a simple schematic of an output filter for a single phase of one of these inverters. So in this, we have an inverter side inductor, a grid side inductor, the capacitor, and then the resistor that goes alongside it. So this whole filter is used to attenuate any kind of switch noise onto the power line, give us a nice clean AC output, and also attenuate any kind of higher order harmonic.
So let's take a close look at actually designing some of these components. So the primary one is going to be the inverter side inductor. There's a fairly generic equation for determining the inductance of this inductor itself. That's going to be VDC over 8 by the frequency of the switching node by the grid rated output current by the allowable ripple percentage.
For this particular design, VDC is 1,000 volts. Our switching frequency is 50 kilohertz. The output current per phase is going to be 18 amps. And then our percent ripple are going to be 40, which we'll talk a little bit more about later how we determine. For the primary filter capacitor, we actually need to know a certain assumption, which is going to be the reactive power absorption.
For this particular design, we're going to use 5%. So that's going to be the percent x factor inside this equation. So we take this absorption by the Q rated, or the output power per phase, which will be 3.3 kilowatts over 2 pi grid frequency by grid voltage. And this gives us an output capacitance of about 10 microfarads.
For the remainder of the filter design, we need to determine the values by defining an attenuation factor between the allowable ripple in the great inductor and the inverter inductor. This factor needs to be minimized while still maintaining a stable and cost-effective total filter solution. By assuming an attenuation factor between these I grid and I inverter values, we can determine this R value, which will lead us and find the value our grid inductance. For this particular design, we've chosen an attenuation factor of 10, which ends up giving us an R value of about 2.7%. This leads to a grid side inductance of approximately 9.2 microhenries based on our earlier design of our inverter side inductor.
One of the factors that we actually don't have shown in the equation here is the filter's resonant frequency. So the filter design can actually be validated by determining its resonant frequency. A good criteria for ensuring a stable resonance is that it is an order of magnitude above the line frequency and less than half of the switching frequency. This criteria avoids issues in the upper and lower harmonic spectrums.
So in this case, since we're using a 50 kilohertz switching frequency, we want our output filter resonance to be below 25 kilohertz and above 50 to 60 hertz. Using the values that we've already determined for the both inductors and the capacitor, we can find that the actual system resonant frequency is approximately 16.7 kilohertz, which falls well within our criteria spectrum. We can then use this resonant frequency to determine the value of Rd, or the final component of our filter itself, using the last equation shown on the left. So it's the inverse of 2 pi by the resonant frequency by Cf all by three. And this is going to give us an output value of Rd of 0.316 ohms.
Now, there were some assumptions that we made inside the design of this filter. Namely, the percent of allowable ripple. So what we can actually look at is the effect that that percent ripple factor is going to have on our output harmonic distortion. So by determining that THD value for each of our different ripple values through this entire chain, we can see that even the difference between using a 10%, 20%, and 40% ripple, all of these are going to be below our specified system ripple allow of 2%.
The primary change here that we can see, though, is that by using a 40% ripple versus a 20% ripple, that we have a significant reduction in the value of our inverter side inductor, which as we mentioned, is going to be the primary size component of this filter design itself. Though it's up to the designer to be able to balance these out and make sure that the filter will meet systems specifications while still maximizing all of the benefits that we want to extract from our system design.
Since it is a primary component of that filter, let's take a closer look at the inductor used for the 50 kilohertz filter. We determined in the previous section that the value of this inductor is going to be 346 microhenries. We also decided based on systems specifications that it's going to be 84 turns of 12 gauge flat wire. This will let us handle the rated and peak currents of 15 and 24 amps, respectively.
We chose a magnetic material, Kool Mu 26, for the actual core of this conductor, and then partnered with Wurth Electronics to design the component itself. And component came up to about 2.4 inches in diameter by 1.5 inches max. And then we were able to determine the AC and DC resistance of the inductor. Once those are determined, we can find the value of the peak inductor loss, which came out to about 5.6 watts per phase.
Now we can compare this if we use standard inductor design formulas. The value of the inductor is actually going to have a significant role to play on the size of it. So as we start to decrease this inductor value, like we saw in the previous slide-- by doubling our switch frequency, we cut our inductance by half-- we can see a similar thing inside the actual volume of the inductor itself. So this is where we can start to really see the benefits of increasing the switch speeds to decrease the filter design component size.
So determining the actual losses of the IGBTs and silicon carbide MOSFETs is fairly well understood. So we're not going to go too deeply into how these were actually calculated. If you would like more information on either of these two loss calculations, please see the full reference design diagram at ti.com. We can add in our inductor losses at 5.64 watts to the IGBT loss of 7.56 watts and the SiC FET loss of 5.63 watts per device. This comes out to a total per phase of 32 watts, or a system total for all three phase of about 96 watts.
So this is, again, using silicon IGBTs, silicon carbide MOSFETs, our custom LCL filter. And we can compare this, now, to our total system power of 10 kilowatts. We can see that once we have this full system designed in, the actual system efficiency is expected to be over 99%.
Now that we have the critical hardware taken care of on this particular design, let's take a little bit closer look at what we can do with the actual control software. So inside the heart of one of these inverters is going to be some kind of a DSP running very tight control systems that's going to enable the inverter to operate efficiently and effectively. And we're going to need the correct components in order to optimize that.
So let's look at the actual requirements of the digital power controller. In choosing a digital power controller for your system, it's important to evaluate four main features. Firstly, the ADC must be able to sample fast enough to stabilize the control loop and should be tightly coupled with the CPU and PWMs for fast control loop response.
The CPU must be high performance enough to compute the necessary control functions, as well as receive input from the ADC and output the control loop behavior to the PWMs within a single control loop cycle. Remember, as we start going faster here, the amount of time that we have to compute that control loop cycle is going to be getting shorter, since the actual time between cycles at 50 kilohertz is significantly shorter than that when we're operating at 15 to 20 kilohertz.
The PWMs on this controller must also be flexible enough to allow for complex topologies and precise synchronization in order to efficiently and effectively control the FETs in the power stage. Particular for this one, now that we have this additional deadband, it's handy to be able to integrate that kind of functionality into a hardware PWM pattern generator. And finally, there must be an on chip comparator that is able to trip PWM outputs for precise control and monitoring of the power stage. All of these combine together to create an effective control system.
Now for the particular design of the TIDA-01606 TI design, we chose to use the Delfino TMS320F2837xD 23:7 processor. This processor features 800 MIPS of real time performance on a dual core C28 platform, has four differential 16-bit ADCs that can sample up to 1 MSPS. It has a built in trigonometric math unit, which lets it accelerate a lot of the control functionality that we're running on the processor.
And then finally, it has 8 sigma delta decimation filters, which enables the input from those isolated AMC sensors that we mentioned earlier straight into the processor's filters, and then into our control loop. In addition, the Delfino class processors come with a digital power SDK, which gives a great framework for getting started, controlSUITE software, and then anything also for safety as well as development environments. If you'd like more information on this particular device or working on evaluating it, please visit ti.com.
Let's take a quick look at the open loop control software that we use to evaluating the actual design itself. So this one is actually pretty straightforward. We'll be using an input frequency and ISR period in order to generate a ramp function. From that ramp function, we'll generate an angle and a sine cosine that will be fed into a DQ0 ABC filter. Alongside an ID ref, value this will generate the PWM outputs for phases A, B, and C.
And inside the actual PWM hardware is where we've already set up the channels for the FETs themselves, and how the different FETs inside the H-bridge and the T-bridge will be complimentary. And so we can use standard three-phase control logic with that PWM hardware in order to generate the three-phase output using standard control system.
Now for open loop control, we don't really need to be concerning ourselves with what the output voltage and current is at this point. However, it is nice to know that we're operating effectively so we can read those in from our ADC hardware and then run them in through an ABC DQ0 in order to evaluate the correct outputs. We can also run this through a PLL for the three-phase and make sure that we're locking appropriately to grid voltage whenever we start testing in that particular application.
Inside the controlSUITE software, we also have functionality for looking at the data logger. So we can log different values coming out of this system, as well as a PWM [? TAC ?] macro that we can pass out through a low pass filter and get a little more granularity on how the system is functioning to make sure that all of our feedback values are being read correctly and we're outputting the correct values into the inverter itself. So really, this open loop control software is really just for evaluating hardware and making sure the right signals are coming into the right place inside the system.
Now the next step is to start closing the control loop. And that's going to be using a grid connected system. Notice the primary difference here is that we're taking these ADC signals and feeding them back into the system itself. So in this particular case, we're going to use VABV and VC and run that into the ABC DQ0 filter into the PLL that we have evaluated and ensured was working and locking correctly earlier.
And that will run back into our DQ0 ABC filter. So what this will effectively do is take the grid level voltages and lock our control system to that frequency so that the output of the inverters is going to match the grid. And we'll also be tracking inverter currents via IA, IB, and IC. Again, running them into an ABC DQ0 filter.
And then that will go into pi macros, which will feed in the DS and DQ values of that DQ0 ABC filter. And this will allow us to complete the control loop. So now we have voltage tracking on the output and current control. So we can essentially have the inverter track the amount of current by referencing it to this ID ref input. So at any point, we can change the actual amount of output current while maintaining a stable voltage.
Now, all of these blocks that we showed previously are going to be integrated inside the actual TI software and provided with the design. So all of these filter blocks have been tested and validated. Additionally, all of the feedback sensing has been validated. The hardware control has been validated. And then basic grid connected current feedback control loop will be implemented inside the design and published alongside it. Advanced features, such as P and Q control for reactive power support, DC bus regulation, unbalanced load control, anti-aliasing-- anti-islanding, and additional safety features, will be left up to the customer to implement and integrate their own particular IP.
Now that we've gone through all of the design criteria, let's finally take a close look at TIDA-01606, a three-level, three-phase, 10 kilowatt silicon carbide solar inverter. At a high level, we've already looked at a lot of these specifications of the inverter itself. An input of 800 to 1,000 volts, an output of 400 volts AC. Valuation of 10 kilowatts peak power, over 99% peak efficiency, and a PWM frequency of 50 kilohertz. We're using the ISO5852S family of gate drivers for the silicon carbide devices, and the UCC5320 gate drivers for the IGBTs.
This particular design is using the Littlefuse LSIC1MO120E0080 1,200 volt 80 milliohm silicon carbide MOSFETs. By switching at 50 kilohertz, we're seeing a significant reduction in output filter size. We have isolated current sensing using AMC1306. Differential voltage sensing using the OPA4350 for low voltage monitoring. And all of this with less than 2% output current THD at full load. Alongside this design, we have all of the design files, including schematics, building materials, analysis, and all of the LTM files for the design, as well as all software that's required to run it inside the tools folder with a full test data and design guide document available for download.
Once again to highlight a few of the key TI parts that we've already talked about that were used inside this design, primarily the ISO58528, which enables us to drive the silicon carbide MOSFETs effectively. It's a 5 by 5 amp, 5.7 kilovolt RMS isolated gate driver. We have the TMS28379D dual core Delfino microcontroller to run all of the digital control algorithms for the three-phase inverter.
And this particular processor is on a control card form factor that the C2000 device family provides for evaluation. So even a different particular product could be used inside this inverter and evaluated to further optimize the system. Also using the AMC130605, a precision 50 millivolt input reinforced isolated amplifier to replace low frequency current transformers like hall or fluxgates for measuring the 50 to 60 hertz current. Then lastly, the OPA4350, a high-speed, single-supply, rail-to-raili operational amplifier for measuring our input and output voltages.
Let's take a little bit of a closer look at the design itself and some of the key hardware. So on the left here, we have the gate drivers that we've actually installed onto a daughter card, the ISO5852 5 with all of its safety features on the left. And then the UCC5320 for the IGBTs on the right. You can see the differences in implementation complexity on the two of these. And with this specific design, if a different gate driver is determined that you want to evaluate, a different gate driver could be designed and installed without having to redesign the entire inverter system itself.
And on the right hand side, we actually have the key of the system itself, the Littlefuse silicon MOSFET devices. And this is just one of the phases. So we can see that H-bridge implemented with the two devices there. And then further behind are the additional phases inside that image. And on the left hand side here, you can actually see the size of the inductor by comparison to these TO-247 packages. So even inside an inverter this large, you can see how big of an impact the size of that filter will have.
We can see the full system shown on the left here in the image. As you can see, there are still some optimizations that could be made when it comes to actual physical layout and design. This could be a lot more compact. But again, this is an evaluation and test platform for Texas Instruments. So [INAUDIBLE] information, please do visit the TI design page for TIDA-01606, where we go into more detail. We have reference material for additional silicon carbide-based designs at tidesigns.com ' that you can check out, and plenty more training available at training.ti.com. Thank you.
May 15, 2018
Increasing demand for renewable energy sources pushing the requirements of higher efficiency and power density which can be achieved at high voltage DC inputs from PV panel. Silicon Carbide (SiC) devices gain advantage over Si IGBT at high voltage due to lower conduction and switching losses. Since PV inverters are typically cooled by natural convection power density is greatly impacted by system losses.With SiC, inverter switching frequency can be 1.5x to 2x times of conventional IGBT switching frequency. Switching high voltage at high switching frequency involves challenges in terms of isolation and regulatory compliance. This session is about design considerations and challenges involved in designing a high power (10kW and higher) SiC based grid-tie inverter.