Demonstrating Simple Open Real-Time Ethernet Protocol (SORTE) Master and Slave on PRU-ICSS using Processor SDK RTOS
Demonstrating EtherCAT Master on Sitara AM57x Gb Ethernet and PRU-ICSS">
IEC 62439-3 HSR/PRP Implementation on Sitara™ Processors using PRU-ICSS">
Description
December 22, 2017
This video demonstrates how to setup and test the Simple Open Real-Time Ethernet Protocol (SORTE) Master and Slave implementation on the Programmable Real-time Unit and Industrial Communication Subsystem (PRU-ICSS). SORTE functionality is supported on Processor Software Development Kits for RTOS, also known as the Processor SDK RTOS.
PDFs for download
Additional information
This course is also a part of the following series
Date: June 23, 2017
Date: July 18, 2018
