April 6, 2019
This video starts with an introduction of electrical overstress, abbreviated EOS, and Electrostatic Discharge, abbreviated ESD. We will look at the difference between ESD and EOS, as well as potential sources of EOS. We will also look at different categories of internal ESD structures used on data converters and give a brief description of their operation and limitations.
1Digital communications basics (6)
Overview of SPI, I2C and parallel communications.
2Introduction to analog-to-digital converters (ADCs) (2)
These videos describe the key specifications listed in an analog-to-digital converter datasheet.
3SAR and delta-sigma: Understanding the difference (4)
This series covers an explanation of the SAR and delta-sigma topology.
4Analog-to-digital converter (ADC) drive topologies (5)
These videos describe the different types front-end topologies that can be used to drive the input signal of an ADC.
5Error sources (3)
These videos describe how to calculate the error and noise of analog-to-digital converters (ADCs).
6ADC noise (13)
This covers analysis, simulation, and measurement of ADC noise for delta sigma and SAR devices.
7AC specifications (5)
These videos describe how to analyze analog-to-digital converter (ADC) performance specifications that are measured using AC input signals.
8Successive-approximation-register (SAR) analog-to-digital converter (ADC) input driver design (8)
These videos describe how to design the input driver circuitry for a SAR ADC.
9Driving the reference input on a SAR ADC (6)
This section covers SAR voltage reference specifications, reference behavior and methods for driving the reference input that minimizes error.
11Electrical overstress on data converters (12)
This series covers methods for protecting a system with an ADC with external components and how to minimize the impact of protection components on performance.
12High-speed analog-to-digital converter (ADC) fundamentals (7)
These videos cover the fundamentals of high-speed data converters, including an overview of the architectures of both ADCs and DACs.