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1.1 Ethernet System Hardware on Sitara AM-Class Processors

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Date: June 30, 2016

This module provides a system perspective of the Ethernet interface on Sitara AM-class processors, from understanding the MAC-PHY relationship to discussing elements such as interface clocking, PHY modes, MAC-to-MAC, and expected scope captures of the MDIO bus and signal bus. It also addresses Ethernet interface layout considerations, including length matching, reference planes, and via spacing.  Overall, this training will develop an understanding of hardware design, as well as common hardware debugging procedures for both board bring up and product development.

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