Email

3.1 Extending JESD204B Link on Low Cost Substrates

Watch the next video in the series:

Details

Date: June 29, 2015

This video discusses the JESD204B SERDES standard related to minimum integrity to maintain proper eye diagram.  As the link length is extended, signal integrity is degraded, but ADC features related to emphasis and de-emphasis can restore optimum operation.

Related courses and events

Delta-Sigma ADCs - Aliasing
Date:
May 4, 2017
TI Precision Labs - ADCs: Voltage Reference Overview
Date:
May 11, 2018
JESD204B training, part 3 of 3: Multi-device synchronization
Date:
April 29, 2016
The Impact of Jitter on Signal to Noise Ratio (SNR) for High-Speed Analog-to-Digital Converters (ADCs)
Date:
July 31, 2017
High Speed Data Converter Signal Processing: Real and Complex Modulation
Date:
September 14, 2017

© Copyright 1995-2018 Texas Instruments Incorporated. All rights reserved.

arrow-topclosedeletedownloadmenusearchsortingArrowszoom-inzoom-out arrow-downarrow-uparrowCircle-leftarrowCircle-rightblockDiagramcalculatorcalendarchatBubble-doublechatBubble-personchatBubble-singlecheckmark-circlechevron-downchevron-leftchevron-rightchevron-upchipclipboardclose-circlecrossReferencedashdocument-genericdocument-pdfAcrobatdocument-webevaluationModuleglobehistoryClockinfo-circlelistlockmailmyTIonlineDataSheetpersonphonequestion-circlereferenceDesignshoppingCartstartoolsvideoswarningwiki