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1.3 Gate Driver Design - from Basics to Details

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Date: October 1, 2018

We live in a world where designers are constantly pursuing higher efficiency. Our customers want more power out with less power in! One result of increased system efficiency is increased power density. The need for higher power densities is a trend seen across isolated and non-isolated power systems. Efficiency is a team effort that includes, but is not limited to, better performing gate drivers, controllers, and transistors. High voltage transistors have seen exponential improvements in new technologies (like SiC-MOSFETS, GaN transistors, Trench/Field-Stop IGBTs, and Super-Junction MOSFETs) and dynamic performance (like switch-transition speed, switching loss and body/anti-parallel reverse recovery). These improvements, however, cannot be fully realized without robust, fast, and smart high voltage gate drivers. These gate drivers are necessary to handle high dv/dt, high di/dt, and fast propagation delays. This in-depth discussion will cover how to drive these state-of-the-art power transistors and key design considerations that our customers face. Topics will include: parasitic influences, hard switching vs soft switching, non-linear junction capacitance (CRSS, COSS), common-mode transient immunity (CMTI), turn-off negative bias, and separating power/ground noise. We will also discuss how TI's gate driver portfolio is addressing the challenges of driving these new transistor technologies.

Additional information

This presentation will cover how to drive state-of-the-art power transistors and key design considerations. Topics will include: Parasitic influences, hard switching vs soft switching, non-linear junction capacitance (CRSS, COSS), common-mode transient immunity (CMTI), turn-off negative bias, separating power/ground noise, and trade-offs between different isolated DC/DC topologies for powering gate drivers.

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