3.3 Get Your Clocks in Sync: Hardware Setup
Description
August 14, 2017
The Multi-Channel JESD204B 15 GHz Clocking Reference Design for DSO, Radar and 5G Wireless Testers is capable of supporting two high speed channels on separate boards by utilizing TI’s LMX2594 wideband PLL with integrated VCOs to generate a 10 MHz to 15 GHz clock and SYSREF for JESD204B interfaces. The 10 KHz offset phase noise is < -104 dBc/Hz for a 15 GHz clock frequency. By using TI’s ADC12DJ3200 high speed converter EVMs, a board-to-board clock skew of <10ps is achieved and a SNR of 49.6 dB with a 5.25 GHz input signal. This video demonstrates: DEV_CLK skew between the two clock outputs of the TIDA-01021 clocking board and the analog channel to channel skew between two ADC12DJ3200EVMs.
Additional information
Other Reference Designs
- Clocking, Power and Analog Front-End (AFE) in One Board: Flexible 3.2-GSPS Multichannel AFE Reference Design for DSOs, RADAR, and 5G
- Clocking Tree Structure: High Channel Count JESD204B Clock Generation Reference Design for RADAR and 5G Wireless Testers
- Clock Daisy Chaining: High Channel Count JESD204B Daisy Chain Clock Reference Design for RADAR and 5G Wireless Testers
