Welcome. My name is Tom Bonifield. I am a high-voltage isolation technologist at Texas Instruments. And we are in one of the high-voltage labs at TI. This video is part of a series of videos on high-voltage reinforced isolation quality and reliability. This video is on the high-voltage isolation structure itself.
Reinforced isolation technology at Texas Instruments is realized by using thick silicon dioxide capacitors combined in series. Each channel uses high-voltage isolation capacitors on both die. As you can see in the schematic cross-section in the upper left, where there is a die on the left side and a die on the right side, and each of them have a high-voltage capacitor. And they're connected in series. The combined isolation capacitor thickness is greater than 21 microns.
Data is transmitted across the isolation barrier, as shown in the schematic on the upper right. Signal comes in, is modulated, goes across the barrier as part of a differential pair of capacitors, demodulated, and out. This same isolation communication path is used for digital isolators, for isolated links, for A to D converters, isolated amplifiers, and isolated gate drivers. The result of this structure is a very high isolation capability, 12.8 kV surge voltage rating, 8 kVpeak transient over-voltage, and 1.5 kVrms working voltage.
Now let's dive into the structure. We'll start at the high level. What you're seeing is an X-ray image of a 16-pin SOIC package. This is a wide-body package in which there is 8 millimeters of creepage and clearance from the top of the picture to the bottom or usually called the left to the right. Inside the package, there's a large internal spacing of greater than 600 microns between the die pads. And on the die pads are two die, one on each side. Each have high-voltage capacitors, as you can see. This is a three-channel isolator, and you can see six capacitors on each side.
Now let's dive into the isolation capacitor in detail. The reinforced isolation barrier consists of two of these high-voltage capacitors, one on each die connected in series. And each capacitor is a thick silicon dioxide capacitor dielectric. The dielectric is made up of multiple layers. Each of the layers is typical of the way integrated circuits are built in billions of units in the industry every year.
Each layer is deposited silicon dioxide, deposited using chemical vapor deposition. Chemical vapor deposition is an atomic molecular deposition that builds up the silicon dioxide film. Before a second layer is added on top of another layer, the first layer is polished with a chemical mechanical polish planarization for good adhesion between layers. The result is a very thick silicon dioxide capacitor greater than 10.5 microns in total thickness for very high isolation voltage capability.
One of the best tests for this is breakdown voltage test or ramp-to-breakdown test. In this test, an AC high-voltage stress is applied from the left side to the right side. That stress is ramped up at a rate of 1 kilovolt rms per second until breakdown occurs. When breakdown occurs, the breakdown voltage is recorded. This is repeated on a large population of units. From the statistics on those units, we can assess how well the technology performs relative to the rating.
So in this graph, this is a histogram of 1,130 units that were tested for ramp-to-breakdown, taken from 113 lots. What you can see is that the average breakdown voltage is greater than 14 kilovolts per rms. That is a lot higher than the isolation rating of 5.7 kVrms.
So a good way to judge how much higher it is is a metric called CPK. CPK of 1 means that the data is 3 sigma above the isolation requirement. A CPK of 2 means that the data is 6 sigma above the isolation rating. And as you can see, this dataset has a CPK greater than 6. And this CPK is measured to the production test condition, which is 20% above the isolation rating.
This data demonstrates very high voltage isolation capability. In conclusion, TI's reinforced isolation family of products has high-voltage capability that exceeds the requirements for reinforced isolation. The quality of the high-voltage isolation is demonstrated by substantial margins using statistical test methods. For more details, you can go to ti.com/isolation to find the white paper enabling high-voltage signal isolation quality and reliability. Thank you. 欢迎。 我是Tom Bonifield。 我是德州仪器的高压隔离 技术专家。 我们现在在TI的一个高压实验室里。 该视频是关于 高压增强隔离质量和可靠性的 一系列视频中的一部分。 该视频位于高压隔离 结构本身。
德州仪器的增强隔离技术 通过使用串联的厚二氧化硅 电容器实现。 每个通道在两个芯片上都使用 高压隔离电容。 正如你可以在左上方的 示意性横截面中看到的那样，左侧有一个模具， 右侧有一个模具，每个模具 都有一个高压电容器。 它们是串联连接的。 组合的隔离电容器厚度 大于21微米。
数据通过隔离栅传输， 如右上方的原理图所示。 信号进入，被调制，作为差分电容器的一部分 穿过屏障，解调 并输出。 这种相同的隔离通信路径 用于数字隔离器，隔离链路， A / D转换器，隔离放大器和隔离栅极 驱动器。 这种结构的结果是具有非常高的隔离 能力，12.8 kV浪涌电压额定值， 8 kV峰值瞬态过电压和1.5 kVrms工作电压。
现在让我们深入了解结构。 我们将从高层开始。 你所看到的是16引脚SOIC封装的X射线图像。 这是一种宽体封装， 其中从图像顶部到底部 有8毫米的爬电距离， 或者通常称为从左到右。 在封装内部，芯片焊盘之间的内部间距 大于600微米。 在芯片垫上有两个芯片，每侧一个。 如你所见，每个都有高压电容器。 这是一个三通道隔离器， 每侧可以看到六个电容器。
现在让我们详细介绍隔离电容。 增强隔离屏障由两个 这样的高压电容器组成，每个 芯片上串联一个。 并且每个电容器都是厚的二氧化硅电容器 电介质。 电介质由多层组成。 每层都是典型的集成电路 每年在数十亿单元中建造的方式。
每层沉积二氧化硅， 使用化学气相沉积进行沉积。 化学气相沉积是原子分子沉积， 其构建二氧化硅膜。 在将第二层添加到另一层之上之前， 用化学机械抛光平面化对第一层进行抛光， 以使层之间具有良好的粘合性。 结果是非常厚的 二氧化硅电容器，总厚度大于 10.5微米，具有非常高的隔离电压能力。
对此最好的测试之一是击穿电压测试 或斜坡到击穿测试。 在该测试中，从左侧向右侧 施加AC高压应力。 这种压力以每秒1千伏rms的 速率上升，直到发生故障。 当发生击穿时，记录击穿电压。 对大量单位重复这一点。 根据这些单位的统计数据， 我们可以评估该技术 相对于评级的表现。
因此，在此图中， 这是一个1,130个单位的直方图， 经过113个批次的斜坡到击穿测试。 你可以看到平均击穿电压 大于每千瓦14千伏。 这比5.7 kVrms的隔离额定值高很多。
因此，判断CPW高度的 一个好方法是CPK。 CPK为1表示数据高于隔离 要求3Σ。 CPK为2意味着数据比隔离额定值 高6Σ。 正如你所看到的，此数据集的CPK大于6。 并且此CPK是根据生产测试条件 测量的，该条件比隔离评级高20％。
该数据表明了非常高的电压隔离能力。 总之，TI的增强型隔离系列产品 具有超出强化隔离要求的 高压能力。 使用统计测试方法 通过大量利润证明了 高压隔离的质量。 有关详细信息，你可以访问ti.com/isolation 查找白皮书，以实现高压信号 隔离质量和可靠性。 谢谢。 This website is under heavy load (queue full) We're sorry, too many people are accessing this website at the same time. We're working on this problem. Please try again later.
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