IMS2015 - JOOS Demo


Date: August 28, 2015

JESD204B is a common standard for implementing a SerDes interconnection between FPGA/Processor and the data converter.  Because the SerDes is operating up to 12.5 Gbps, the interconnect integrity is critical to maintain proper data transfer.  There are specific requirements that limit the physical length of the JESD204B transmission lanes.  What do you do if the data converters must be physically separated from the FPGA/Processor?  Introduce the "JOOS" (JESD204B Over Optical System).  The JOOS platform demonstrates how to connect a JESD204B link across an optical network and maintain signal integrity and deterministic latency so that the transceivers can be very far removed from the BB processing.

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