Interfacing multiple analog-to-digital converters on a Sitara™ processor

This series demonstrates how to use the PRU-ICSS subsystem on a Sitara processor to interface between multiple SAR ADCs using SPI.

In this training series, we demonstrate how to use the PRU-ICSS subsystem on a Sitara™ processor to interface between multiple SAR analog-to-digital converters (ADC) using serial peripheral interfaces (SPI).

Applications like protection relay and grid automation use multiple ADCs with SPI to acquire data from various voltage and current transducers. This, along with the need for adding redundant channels for reliability, is driving the need for expanding the input channels that should all be synchronized on the data acquisition (DAQ) system. With limited SPI peripherals and data-capture rate in micro-controllers, interfacing multiple ADCs becomes difficult. With a high-performance ADC — like those found on Sitara processors — engineers can achieve better accuracy. The challenge is in synchronizing, simultaneous sampling, and achieving coherency (sampling the same number of samples for varying input frequency). We'll show you how to address these topics in this training series.

Our Flexible Interface (PRU-ICSS) Reference Design for Simultaneous, Coherent DAQ Using Multiple ADCs is an elegant solution for interfacing multiple SAR ADCs to achieve synchronization and simultaneous sampling. We use six ADCs with mux inputs to keep the cost low. Each ADC runs at 256 ksps (32 ksps/channel and 1536 ksps across six ADCs). The sampling rate can be easily adjusted to meet IEC61850-9-2 standard for protection and measurement. The PRU-ICSS subsystem provides the ability to dynamically adjust the ADC interface timing and thereby extract the highest AC performance from ADCs resulting in more accurate data acquisition. Also, using the zero-cross detect scheme, coherency is achieved by adjusting the sampling rate of the ADC which simplifies hardware design.

Additional information

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