Three-part JESD204B training series
This three-part training series introduces fundamentals and tips for leveraging the JESD204B serial interface standard, which provides board area, FPGA/ASIC pin-count and deterministic latency improvements over traditional LVDS and CMOS interfaces. TI’s JESD204B ADCs, DACs, clock ICs and development tools enable quick evaluation, design and implementation of designs utilizing the JESD204B interface. Learn more today through this on-demand series.
Questions? Visit the high-speed page of TI’s E2E Community for a quick response! Visit http://e2e.ti.com/support/data_converters/high_speed_data_converters/. If you click on a specific part, you can submit a question to the supporting team.