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パワーサプライ・デザイン・セミナー 2018 シリーズ
クラス D オーディオ・アンプの 電源ソリューション（英語） AC/DC Power Solutions for Class-D Audio Amplifiers
パワーサプライ・デザイン・セミナー 2018 シリーズ
4.3 AC/DC Power Solutions for Class-D Audio Amplifiers
[MUSIC PLAYING] Now let's move on to part three of the presentation, which talks about the AC to DC power supply. In this section, we will discuss how to select the main parameters of an AC to DC power supply suitable for supplying power for Class-D audio amplifiers.
In the bullets on this slide, there's a short list of test parameters, like universal input voltage, good transient response-- according to the requirement calculated in the previous section-- and good light load efficiency for low consumption at very low or muted volume. The PFC stage, or power factor correction stage, is needed here because the average input power is higher than 75 watts, even when considering your power ratio of 8 to 1.
The block diagram on the bottom right corner shows the main blocks of the power supply. The first block is the PFC AC to DC converter producing 400 volts. The second stage is an isolated DC to DC converter with an auxiliary power supply. The average output power of this power supply is 200 watts.
For the PFC stage, we considered four different types of boost converters, as shown here in this slide. Interleaved transition mode and single-phase continuous conduction mode are suitable here. And the single-channel CCM has the advantage because it can be scaled to a higher power level, while interleaved CCM is typically employed at power levels higher than 800 watts. Because we are designing power around 200 to 400 watts peak, we land in the middle region of the slide. For this reason, we selected the low-cost UCC28180 controller, which is a single-phase continuous conduction mode controller.
The bandwidth of the power factor correction stage must satisfy several constraints. So it must be carefully selected and should not be too high. Otherwise, the controller will try to follow the output ripple voltage.
In the bottom right corner, we see the green VPFC line, which is the voltage of the power factor correction. Since the controller tries to follow the ripple, it will distort the input current of the power factor correction stage. This increase in the distortion of the AC input current results in worsening the THD and the power factor. On the other hand, small loop bandwidth makes the PFC stage react more slowly to load transients. However, we can't select a bandwidth too low because this can cause high output overvoltage and undervoltage events that would be harmful for active and passive components-- mainly, the MOSFETs, the diodes, as well as the capacitors.
The output of the PFC stage becomes the input of the next stage. So these resulting occurrences from a low bandwidth can affect the next stage as well. It can be demonstrated that an attenuation of the closed loop gain at 100 or 120 hertz higher than the 20 dB is already enough to keep input current harmonics inside the EN 61000-3-2 limits. A similar constraint comes from the interaction between minimum frequency of an audio signal, which is 20 hertz, and twice the line frequency.
The bottom right corner of the screen shows the output current-- the yellow trace-- and the PFC stage voltage-- the green trace-- which will supply the DC to DC converter downstream, which then supplies the audio amplifier. At 20 hertz, or the ripple current at 40 hertz, the current swings from zero to twice the DC current. This is proportional to the average output power.
It's important to select the crossover frequency of the PFC stage according to the formula on the top left corner. This way, the PFC stage delivers only the average power rather than the peak power. Therefore, the whole power stage can be sized dimensionally for a lower power rating.
It's important to select enough output capacitance to avoid triggering the internal EDR threshold. The EDR is the enhanced dynamic response, which is plus or minus 5%, as we can see here in the graph below. If there isn't enough output capacitance, heavy distortion can appear and worsen the total harmonic distortion and power factor.
So which is the best topology for this DC to DC power stage? There are several possibilities to consider. A few are listed here in this table. More are listed in the white paper.
Because the flyback is suitable for continuous output power of only up to 100 watts, we analyzed the half-bridge, the two-switch forward, and the LLC resonant topololgies. The LLC topology is not in this table, but it's explained in more detail in the white paper. We don't want to discuss all advantages and disadvantages over every topology, but in the end, we selected the two-switch forward topology because it's a low-cost solution. The voltage stress on each main FET is only VIN. And the transformer demagnetizes itself automatically if the duty cycle is kept less than 50%.
In this slide, we show a simplified schematic of a two-switch forward converter. As you can see here in the simplified schematic, D1 and D2 discharge the energy stored in the core of the transformer each cycle by recovering this energy back to VIN. So this energy is not lost. They also clamp each switch node-- switch one and switch two-- to VIN. This way, Q1 and Q2 FETs have a low-voltage rating, typically 500 or 600 volts.
The controller used was the LM5021, which is a peak current mode controller. It features very low startup current and skip-cycle mode for low standby power, thus improving light load efficiency. Here, both Q1 and Q2 have to be driven simultaneously, which is the opposite of what we do on a half-bridge converter. We do this by directly driving Q2 with a modulator and Q1 by using a gate drive transformer. These are typical low-cost solutions.
In order to avoid transient spikes on Q1 during burst motor skip-cycle mode and to reduce switching losses by driving both FETs with high gate currents, we decided to use floating high- and low-side drivers. These drivers are typically found in half-bridge and full-bridge topologies where the switch node is pulled to ground as soon as the low-side switch is driven. This is normally enough to recharge the CBOOT, or bootstrap capacitor, in each cycle.
In the two-switch forward topology, we have two switch nodes-- switch one and switch two. As soon as Q2 is driven on and switch two reaches 0 volts, the capacitor CBOOT recharge is only when switch one reaches 0 volts, which occurs when Q1 is switched off. This is the opposite of what happens in the half-bridge. CBOOT also recharges if there is enough energy in the magnetizing current to charge the COSS of Q1 and the interwinding capacitance of the transformer, as shown in the picture in the bottom right corner.
If the actual TON is very small-- for example, during light-load DCM or burst mode-- the stored magnetizing energy would not be enough, and the switch one valley point will never reach 0 volts. Therefore, in all these valley points, CBOOT will not be recharged. To overcome this issue, we've added a recharge network comprised of an inexpensive small-signal 600-volt SOT-223 FET, which is Q11, shown here. The FET Q12 is an inverter. The network D22, R68, and C51 delays the on time of Q11 in order to turn on Q11 at the valley of the switching waveform.
In the graph on the left, we have shown three signals. The first one is the output of the modulator. It is then delayed and inverted to drive Q11. This network and the associated delay forces switch one to reach ground when the voltage swing reaches the valley.
By switching at the valley, as we know from quasi-resonant converters and controllers, Q1 COSS losses are further reduced. And the delay needed to switch at the valley is calculated using a formula on the first bullet here. The only disadvantage of such a network is that even though Q2 has zero voltage transition during TON, Q1 sees the whole VPFC voltage. Therefore, there is about a 20% to 30% switching loss imbalance between Q1 and Q2.
As previously mentioned, we assume five kilohertz crossover frequency or bandwidth as a starting point of a DC to DC stage. To fulfill the output ripple current requirement, we selected 200 kilohertz as a switching frequency and thus used an output inductor with an LOUT equal to 50 microhenries. To keep the total harmonic distortion of the Class-D audio amp below 0.016%, we can calculate a minimum COUT value according to this formula, which gives a small value of 16 microfarads, or two ohms, as the maximum allowed output impedance of the power supply.
The other two constraints for output capacitance are overshoot and undershoot voltages on VOUT. According to the table in slide 16, assuming the nominal PVDD of the TPA3251EVM is 36 volts, the maximum absolute value is 38 volts, and the maximum duty cycle just before clipping is 95%. With all these numbers, we arrived at the following values of a delta VOVERSHOOT and a delta VUNDERSHOOT. Using these values, we can calculate the minimum output capacitance requirements for the current and voltage modes, respectively 164 microfarads and 321 microfarads.
The output capacitance chosen should be the highest value calculated from these three formulas, which in this case is 321 microfarads. After selecting COUT, and considering the typical ESR values from a high-quality 300 microfarad capacitor, it's possible to choose poles and zeros for the compensation network.
We selected the controller and know that it operates in peak current mode control. So we'll use type II compensation, as shown here. After analyzing poles and zeros of the power stage, we used the components highlighted here in red. A zero has been placed at 184 hertz, and a pole has been placed at 184 kilohertz, which is a typical filter. Our phase margin was 60 degrees, and the Bode plot is shown in the bottom right corner.
The Class-G circuit highlighted in teal is used for over temperature protection. We placed a temperature sensor with a digital output set to 80 degrees close to the main heat sink. The circuit switches between 36 and 18 volts, [? answering ?] Class-G mode when an over temperature condition occurs. Since we have half of the PVDD voltage on the audio amplifier, the power supply is thermally protected because the audio amplifier delivers only 1/4 of the nominal power. We also avoid switching the system completely off, which is undesirable from a user's point of view.
So at this point, COUT, LOUT, and the compensation network are defined. The whole converter has been tested and built, and the low transient response has been verified. COUT was implemented by using three electrolytic capacitors in parallel. Each one is 100 microfarads with an ESR of 74 milliohms. 110 microfarad capacitor has been added to reduce high frequency spikes due to the ESL of the electrolytic capacitors.
The formulas here on the left calculate the output impedance for both the reactive and resistive parts. According to the values that we calculated, we can expect that the load transient response shows a delta V of about 2.4%, which we actually measure by switching the load between 1 and 10 amps, as shown in the screenshot.
Now for the final results. We tested the whole system plus the audio amplifier and power supply in different conditions before working on this presentation and at different frequencies with higher output capacitance. This was before all of the analysis that we made in this topic. And at that time, there was 3,000 microfarads of output capacitance. This output capacitance value was obtained by a specification from the customer, who wanted to have the lowest output impedance and who also wanted to use this power supply with different amplifiers, both Class-D open and closed loop as well as Class-AB amplifiers.
So the first prototype was more general when compared to this analysis. The results are shown in this slide. The efficiency curve shows big improvement between 10 and 50 watts of output power if Class-G is activated.
The comparison here on the right side shows a little harmonic distortion when we use a reference lab supply, as shown in the red on top. You can see that between 10 and 100 watts, the reference lab supply has slightly lower total harmonic distortion compared to our power supply. We've shown total harmonic distortion measurements of the whole system versus power on the top right and versus frequency at different power levels on the bottom right. The only small difference we realized between the reference lab supply and PMP10215 was in the region between 10 and 100 watts.
2018年 2月 8日
This training series describes how to properly design a power supply for a high-power Class-D amplifier based on the output impedance requirements as well as on typical requirements like average and peak power demands. In this video, we explore an AC/DC power reference design with applications in a Class-D amplifier and sound bar.