Get Your Clocks in Sync: Hardware Setup
説明
2017年 8月 14日
| This video demonstrates: DEV_CLK skew between the two clock outputs of the TIDA-01021 clocking board and the analog channel to channel skew between two ADC12DJ3200EVMs. |
追加情報
Other Reference Designs
- Clocking, Power and Analog Front-End (AFE) in One Board: Flexible 3.2-GSPS Multichannel AFE Reference Design for DSOs, RADAR, and 5G
- Clocking Tree Structure: High Channel Count JESD204B Clock Generation Reference Design for RADAR and 5G Wireless Testers
- Clock Daisy Chaining: High Channel Count JESD204B Daisy Chain Clock Reference Design for RADAR and 5G Wireless Testers
