LMK03328 ultra low jitter clock generator step by step design-in process
This 3-part video series outlines the design process for the LMK03328 ultra-low-jitter clock generator. The series covers the WEBENCH Clock Architect design and simulation process, using the TICS Pro EVM GUI software with WEBENCH design report to help configure the LMK03328 EVM, frequency planning techniques, and using TICS Pro to program multiple startup profiles to the device EEPROM.
A networking switch clocking example is discussed through the video series to highlight key features and benefits of the LMK03328 Dual PLL clock generator, such as ultra-low phase noise/jitter to improve system performance/margin, EEPROM pin modes to support multiple startup profiles and system validation testing, and flexible frequency planning and frequency margining capabilities.
This design process is also applicable to the LMK03318 (Single PLL version of the LMK03328).