The TPS7H3301-SP is the first double-data-rate (DDR) memory-termination LDO for space applications.

TI’s broad portfolio of enhanced products provide ruggedized components in plastic packaging. Learn about the qualification process and more.

The ADC32RF45 is a dual channel, 14-bit, 3-GSPS ADC. This video shows how the ADC32RF45 supports 1-GHz signal bandwidths and beyond for next generation systems.

This video discusses the sampling clock phase noise performance and how its performance over frequency offset impacts the GSPS ADC SNR performance.

This video discusses the three subclass modes in the JESD204B standard.  The pros and cons of operating in each subclass is discussed.

Introduction to the RF sampling architecture in contrast to traditional direct conversion architectures typically used in existing transceivers.

This video specifically addresses the benefits and advantages RF sampling provides that was limited or not possible with existing technology.

RF Sampling requires fast sampling rates, but the input data rates usually cannot keep pace.  The techniques to mitigate those limitations are addressed.

This video illustrates synchronizing two ADC12J4000 ADCs employing JESD204B interface

Optimize Synthetic Aperture Radar, or SAR, with TI’s integrated 66AK2L06 system-on-a-chip. The FPGA alternative is a KeyStone-based device with a JESD204B inte

Engineers Ken Chan and Ebenezer Dwobeng demonstrate the capabilities of TI's giga-sampling ADC. They use the ADC12J4000 to sample an input signal of 2.14GHz at

TI's new Channel Link Ser/Des families combine high-speed video, clock, and bi-directional control signals over a single twisted wire pair.

Introduction to TI's DS90UR905/906 FPD-Link II automotive-qualified display interface SerDes for 24-bit color depth, higher resolution displays.