Learn about the JESD204B compliant high speed multichannel synchronized clocking architecture

Learn about the high speed multi-channel clocking requirements and challenges.

How to select proper serializer and deserializer for the signal transmission in the relevant applications of human-machine interface (HMI).

Learn how TI’s solutions can help you overcome common power design challenges.

This video will explore a reference design that shows how to synchronize multiple high-speed JESD204B data converters.

This video demonstrates DEV_CLK skew between two clock outputs of the clocking reference design and the analog channel to channel skew between 2 ADC12DJ3200EVMs

This video demonstrates the software setup of the Multi-Channel JESD204B 15 GHz Clocking Reference Design for DSO, Radar and 5G Wireless Testers

Learn how to read a SMD (Standard Microcircuit Drawing) part number.

Learn the basics of a DC/DC SEPIC converter, its advantages compared to other DC/DC topologies, and how a SEPIC can help you in your Automotive display design.

The TPS7H3301-SP is the first double-data-rate (DDR) memory-termination LDO for space applications.

TI’s broad portfolio of enhanced products provide ruggedized components in plastic packaging. Learn about the qualification process and more.

The ADC32RF45 is a dual channel, 14-bit, 3-GSPS ADC. This video shows how the ADC32RF45 supports 1-GHz signal bandwidths and beyond for next generation systems.

This video discusses the sampling clock phase noise performance and how its performance over frequency offset impacts the GSPS ADC SNR performance.

This video discusses the three subclass modes in the JESD204B standard.  The pros and cons of operating in each subclass is discussed.

Introduction to the RF sampling architecture in contrast to traditional direct conversion architectures typically used in existing transceivers.