This presentation covers I2C clock stretching, bus arbitration, logic level translation, and selection of pull-up resistors on an I2C system.

This video convers SPI timing requirements such as setup, hold, and delay time.

This video covers a step-by-step decision tree to help find the best converter for your application.

This video covers the impact that voltage reference noise has on overall ADC converter system performance, and focuses in on how input signal effects the refere

See how to increase signal detection capability in industrial applications, with the new ADC3660 family of SAR ADCs.

Watch this webinar to learn how to design an analog front end for building in-vitro systems of the future.

Describes how a system’s voltage reference interacts with amplifier and PGA gain to determine the overall system performance.

Demo of the JESD204B in space ADC and FPGA, using the Alpha Data Xilinx XQRKU060 development kit with TI ADC12DJ3200

This video covers the noise and drift implications of using a ratiometric reference configuration, vs internal and external.

This getting started video describes the installation, setup, and execution of the ADC-TEMP-SENSOR-FW application software.

This session provides details on the need to focus on the AC analog input module (AIM) and its use cases in different types of protection relays.

New Product Update: New precision wideband ADC

This video introduces the advantages that the JESD204B standard provides in high speed data converters

This video illustrates synchronizing two ADC12J4000 ADCs employing JESD204B interface

This video discusses the JESD204B SERDES standard related to minimum integrity to maintain proper eye diagram. 

Introduction to the RF sampling architecture in contrast to traditional direct conversion architectures typically used in existing transceivers.

This video specifically addresses the benefits and advantages RF sampling provides that was limited or not possible with existing technology.

RF Sampling requires fast sampling rates, but the input data rates usually cannot keep pace.  The techniques to mitigate those limitations are addressed.

A comparison between two of the most common precision analog-to-digital converter (ADC) architectures: successive approximation register and delta-sigma