This video will explore a reference design that shows how to synchronize multiple high-speed JESD204B data converters.

The 105-MHz, OPA837 ultra-low-power amp is well-suited for use as a low-power 12 to 16-bit SAR ADC driver and for ultra-low-power active filter designs.

The 300-MHz gain bandwidth product, OPA838 voltage feedback amp is well-suited for use as a low-power 12 to 14-bit SAR ADC driver or transimpedance amp.

This video demonstrates DEV_CLK skew between two clock outputs of the clocking reference design and the analog channel to channel skew between 2 ADC12DJ3200EVMs

This video demonstrates the software setup of the Multi-Channel JESD204B 15 GHz Clocking Reference Design for DSO, Radar and 5G Wireless Testers

Overview of high-speed data converter architectures: pipeline, interleaved, Successive Approximation Register (SAR), DAC current source and current sink.

Learn more about subsampling concepts pertaining to bandwidth vs. frequency, including: Nyquist frequency, aliasing, under-sampling, and input bandwidth.

Considerations of Clock jitter, the impact on SNR, how to calculate it and minimize noise degradation for High-Speed Analog-to-Digital Converters.

Explore the differences between sample rate and data rate and use decimation or interpolation to decrease or increase the data rate.

Concepts of Signal to Noise Ratio and Noise Spectral Density; an example on how NSD is used to estimate the DAC output as it pertains to noise floor.

LMH3401 7-GHz, fully differential ultra-wide band amplifier provides a fixed gain of 16 dB and is well suited for use in DC to radio frequency applications.

High Precision Digital to Analog Converter Training with Signal High-Fidelity Source Evaluation Module showcases our most precise data converter, the ADS8900B.

This training discusses real-world system requirements for a multi-channel 4-20mA analog input module for programmable logic controller (PLC).

This video will provide an overview of delta-sigma ADC topology.

This video will talk about matching networks and clocking requirements for GSPS and RF Sampling ADC Inputs.

Welcome to this training series on “Designing with delta-sigma ADCs: system design considerations to optimize performance.”

This video will focus on the ADC’s clock input.