ヒント:複数の語句はコンマで区切ってください

入力例:06/25/2022

入力例:06/25/2022

ヒント:複数の語句はコンマで区切ってください

入力例:06/25/2022

入力例:06/25/2022

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291 結果

How to measure RTDs with Delta-Sigma ADC

日付:
2018年 4月 8日

所要時間::
03:55
Precision temperature measurement with Delta-Sigma analog-to-digital converters

Precision temperature measurement in heat and cold meters

How to use our ADS1220 Delta-Sigma converter family for precise temperature measurement in heat and cold meter applications with standard RTDs.
Optimize Your RF Sampling ADC Receiver Performance with the Frequency & Sample Rate Planning Calculator

Optimize RF sampling ADC receiver performance with the frequency & sample rate planning calculator

日付:
2018年 4月 6日

所要時間::
34:18
This video will go over what ADC SFDR's are, explain the concept of frequency planning and provide tools to help with RF sampling design. 

Hands-on experiment: Amplifier settling and charge bucket filter design

日付:
2018年 3月 16日

所要時間::
22:03
This hands-on experiment shows how to simulate ADC settling time and then measure the impact different amplifiers and charge buckets have on THD and SNR.

Hands-on experiment: Aliasing and anti-aliasing filters

日付:
2018年 3月 6日

所要時間::
24:55
This hands-on experiment demonstrates aliasing and the effect of anti-aliasing filters.

Introduction and Hardware Setup for Precision Labs Pro Online Labs

日付:
2018年 1月 26日

所要時間::
18:57
This video is part of the TI Precision Labs – ADCs curriculum. It describes Precision Labs Pro and the steps required to setup the hardware for the online lab e

Hands-on experiment: Crossover distortion on ADC drive

日付:
2018年 1月 19日

所要時間::
11:37
This hands-on experiment shows how the front-end driver impacts SAR ADC performance.

Hands-on experiment: ADC noise

日付:
2018年 1月 19日

所要時間::
16:35
This hands-on experiment shows how the front-end driver is impacted by resistor thermal noise.
TIPL4707 Frequency planning, sampling vs Nyquist, vs harmonics, spurs, etc

Understanding sampling, Nyquist zones, harmonics and spurious performance in high-speed ADCs

日付:
2017年 10月 4日

所要時間::
04:25
The concepts and benefits of frequency planning for high speed ADC systems are covered, including sampling rate vs. Nyquist, harmonics and spurs.
Real and Complex Modulation

High-speed data converter signal processing: Real and complex modulation

日付:
2017年 9月 14日

所要時間::
15:45
This video covers phase and amplitude modulation, introduces the concepts of real and complex modulation and provides an example modulation use case.
SAR ADC Power Scaling

SAR ADC power scaling

日付:
2017年 9月 11日

所要時間::
18:54
This video highlights the considerations for low-power system design.  

Get Your Clocks in Sync for JESD204B Data Converters

日付:
2017年 9月 6日

所要時間::
19:17
This video will explore a reference design that shows how to synchronize multiple high-speed JESD204B data converters.

OPA837 Ultra-Low-Power High-Speed Amplifier Overview

日付:
2017年 8月 22日

所要時間::
04:48
The 105-MHz, OPA837 ultra-low-power amp is well-suited for use as a low-power 12 to 16-bit SAR ADC driver and for ultra-low-power active filter designs.

OPA838 Decompensated High-Speed Amplifier Overview

日付:
2017年 8月 22日

所要時間::
04:13
The 300-MHz gain bandwidth product, OPA838 voltage feedback amp is well-suited for use as a low-power 12 to 14-bit SAR ADC driver or transimpedance amp.

Get Your Clocks in Sync: Hardware Setup

日付:
2017年 8月 14日

所要時間::
02:31
This video demonstrates DEV_CLK skew between two clock outputs of the clocking reference design and the analog channel to channel skew between 2 ADC12DJ3200EVMs

Get Your Clocks in Sync: Software Setup

日付:
2017年 8月 7日

所要時間::
04:20
This video demonstrates the software setup of the Multi-Channel JESD204B 15 GHz Clocking Reference Design for DSO, Radar and 5G Wireless Testers

Comparing high-speed analog-to-digital (ADC) and digital-to-analog (DAC) converter architectures

日付:
2017年 8月 2日

所要時間::
18:40
Overview of high-speed data converter architectures: pipeline, interleaved, Successive Approximation Register (SAR), DAC current source and current sink.
Jitter vs SNR for High Speed ADCs

Jitter's impact on signal-to-noise ratio (SNR) for high-speed analog-to-digital converters (ADCs)

日付:
2017年 7月 31日

所要時間::
08:00
Considerations of Clock jitter, the impact on SNR, how to calculate it and minimize noise degradation for High-Speed Analog-to-Digital Converters.
Bandwidth vs Frequency(Subsampling Concepts)

Bandwidth vs. Frequency - Subsampling Concepts

日付:
2017年 7月 31日

所要時間::
09:17
Learn more about subsampling concepts pertaining to bandwidth vs. frequency, including: Nyquist frequency, aliasing, under-sampling, and input bandwidth.
Understanding Sampling Rate vs Data Rate, Decimation (DDC) and Interpolation (DUC) Concepts in High Speed Data Converters

Sampling vs. data rate, decimation (DDC) and interpolation (DUC) in high-speed data converters

日付:
2017年 7月 31日

所要時間::
18:41
Explore the differences between sample rate and data rate and use decimation or interpolation to decrease or increase the data rate.
291 結果
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