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複数クロックの同期：ハードウェア設定
日付:
所要時間：:
2017年 12月 19日
所要時間：:
02:31
このビデオはTIDA-01021 の 2 つのクロック出力間の DEV_CLK スキュー、2 個の ADC12DJ3200EVM のアナログ・チャネル間スキューを解説します。
TI Precision Labs - Clocks and Timing: Clocking JESD204B/C Systems
日付:
所要時間：:
2020年 6月 30日
所要時間：:
10:07
Clocking JESD204B or JESD204C systems.
TI Precision Labs - Clocks and Timing: System Design Considerations
The videos in this series will discuss distributed vs. centralized clock tree, synchronous vs. free-running designs and other selection criteria requirements to help narrow down a clock tree solution. We will discuss other design considerations including frequency planning, spurious and EMI noise reduction techniques, system clock optimization/tuning and clocking for JESD204 B/C systems.
Reduce design risk for Low Earth Orbit satellites and other New Space applications
日時： 2019年 10月 8日 14:00
What is NewSpace? What does it mean for satellite design? Explore products that meet quality & reliability requirements for short space flights and LEO designs.
Clocking Solutions for High Speed Multi-Channel Applications
Explore clocking solutions for a variety of high speed multi-channel applications.
TI's Bulk Acoustic Wave Clocking Technology
日付:
所要時間：:
2019年 2月 25日
所要時間：:
03:02
This video details TI’s Bulk Acoustic Wave (BAW) clocking technology, optimized to improve network performance, reduce BOM and increase immunity to interference
TI's Bulk Acoustic Wave Clocking Technology
日付:
所要時間：:
2019年 2月 22日
所要時間：:
03:02
This video details TI’s Bulk Acoustic Wave (BAW) clocking technology, optimized to improve network performance, reduce BOM and increase immunity to interference
Better Clocking for Serial Link Applications: TI's BAW-Based LMK05318
日付:
所要時間：:
2018年 12月 11日
所要時間：:
04:27
This video provides an overview of TI's BAW-based network synchronizer clock device and its benefits in clocking 400G serial link applications.
Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 3
日付:
所要時間：:
2018年 7月 25日
所要時間：:
11:22
Learn about the high channel count clocking solution.
Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 2
日付:
所要時間：:
2018年 7月 25日
所要時間：:
09:56
Learn about the JESD204B compliant high speed multichannel synchronized clocking architecture
How to synchronize high speed multi-channel clocks?
Modern high speed end equipment's like oscilloscope, 5G wireless communication tester and RADAR requires multichannel transceiver system. The biggest challenge is to provide the high frequency, low phase noise, multiple synchronized clocks to each transceiver's data converters and local oscillator. This training will explain how to synchronize the high speed multi-channel clocks and expand for high channel count clocks requirement.
Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 1
日付:
所要時間：:
2018年 7月 17日
所要時間：:
07:50
Learn about the high speed multi-channel clocking requirements and challenges.
Hitless Switching with DPLL Network Clock Synchronizers from TI
日付:
所要時間：:
2018年 3月 27日
所要時間：:
01:18
Hitless Switching: Watch how our innovative phase cancellation eliminates phase hits in clock applications.
TI Solutions for Clock and Timing
日付:
所要時間：:
2017年 12月 7日
所要時間：:
15:08
Learn about solutions to common aerospace and defense design challenges to help you simplify designs and improve performance.
Get Your Clocks in Sync for JESD204B Data Converters
日付:
所要時間：:
2017年 9月 6日
所要時間：:
19:17
This video will explore a reference design that shows how to synchronize multiple high-speed JESD204B data converters.
Get Your Clocks in Sync: Hardware Setup
日付:
所要時間：:
2017年 8月 14日
所要時間：:
02:31
This video demonstrates DEV_CLK skew between two clock outputs of the clocking reference design and the analog channel to channel skew between 2 ADC12DJ3200EVMs
Get Your Clocks in Sync: Software Setup
日付:
所要時間：:
2017年 8月 7日
所要時間：:
04:20
This video demonstrates the software setup of the Multi-Channel JESD204B 15 GHz Clocking Reference Design for DSO, Radar and 5G Wireless Testers
Design Considerations for Robust Interface Between J6 and Car Displays via FPD-Link [Part 3]
日付:
所要時間：:
2017年 4月 21日
所要時間：:
03:14
Clock cleaners can be incorporated into a system design if jitter issues continue after PCB guidelines and followed and PLL configurations are optimized.
LMK03328 Frequency Margining and EEPROM programming with TICS Pro GUI
日付:
所要時間：:
2017年 1月 13日
所要時間：:
04:41
LMK03328 frequency margining example for generating multiple frequency plan configurations (nominal, margin high, and margin low) and programming these to the E
LMK03328 EVM Setup and Programming with TICS Pro GUI
日付:
所要時間：:
2017年 1月 13日
所要時間：:
08:50
EVM setup and programming using TICS Pro GUI with WEBENCH clock design report to configure and program the device. The video also covers frequency planning tec