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複数クロックの同期:ハードウェア設定
日付:
所要時間::
2017年 12月 19日
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02:31
このビデオはTIDA-01021 の 2 つのクロック出力間の DEV_CLK スキュー、2 個の ADC12DJ3200EVM のアナログ・チャネル間スキューを解説します。
システム性能の最適化と設計時間 超低クロック・ジェネレータ LMK03328
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2016年 1月 13日
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07:12
今日はTIの最新クロック・ジェネレータLMK03328の性能および機能に関するデモをお見せします。
System design considerations
This video series will cover clocks and timing system design considerations such as clock tree design, frequency planning and noise reduction.
Clocking solutions for high-speed multi-channel applications
Learn more about clocking solutions for high-speed multi-channel applications.
TI's Bulk Acoustic Wave Clocking Technology
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所要時間::
2019年 2月 25日
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03:02
This video details TI’s Bulk Acoustic Wave (BAW) clocking technology, optimized to improve network performance, reduce BOM and increase immunity to interference
TI's Bulk Acoustic Wave Clocking Technology
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所要時間::
2019年 2月 22日
所要時間::
03:02
This video details TI’s Bulk Acoustic Wave (BAW) clocking technology, optimized to improve network performance, reduce BOM and increase immunity to interference
Better Clocking for Serial Link Applications: TI's BAW-Based LMK05318
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所要時間::
2018年 12月 11日
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04:27
This video provides an overview of TI's BAW-based network synchronizer clock device and its benefits in clocking 400G serial link applications.
Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 3
日付:
所要時間::
2018年 7月 25日
所要時間::
11:22
Learn about the high channel count clocking solution.
Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 2
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所要時間::
2018年 7月 25日
所要時間::
09:56
Learn about the JESD204B compliant high speed multichannel synchronized clocking architecture
How to synchronize high speed multi-channel clocks?
This training explains how to synchronize high speed multi-channel clocks used in high-speed end equipment with multi-channel transceiver system.
Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 1
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2018年 7月 17日
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07:50
Learn about the high speed multi-channel clocking requirements and challenges.
Hitless Switching with DPLL Network Clock Synchronizers from TI
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2018年 3月 27日
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01:18
Hitless Switching: Watch how our innovative phase cancellation eliminates phase hits in clock applications.
Get Your Clocks in Sync for JESD204B Data Converters
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2017年 9月 6日
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19:17
This video will explore a reference design that shows how to synchronize multiple high-speed JESD204B data converters.
Get Your Clocks in Sync: Hardware Setup
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2017年 8月 14日
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02:31
This video demonstrates DEV_CLK skew between two clock outputs of the clocking reference design and the analog channel to channel skew between 2 ADC12DJ3200EVMs
Get Your Clocks in Sync: Software Setup
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所要時間::
2017年 8月 7日
所要時間::
04:20
This video demonstrates the software setup of the Multi-Channel JESD204B 15 GHz Clocking Reference Design for DSO, Radar and 5G Wireless Testers
LMK03328 Frequency Margining and EEPROM programming with TICS Pro GUI
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2017年 1月 13日
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04:41
LMK03328 frequency margining example for generating multiple frequency plan configurations (nominal, margin high, and margin low) and programming these to the E
LMK03328 EVM Setup and Programming with TICS Pro GUI
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2017年 1月 13日
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08:50
EVM setup and programming using TICS Pro GUI with WEBENCH clock design report to configure and program the device. The video also covers frequency planning tec
TX Signal Chain Implementation for Wide Band and High Frequency Signal Generation
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所要時間::
2016年 11月 10日
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13:45
The system design for an arbitrary waveform generator (AWG) and its functional blocks, including a discussion of the AWG amplifier path and design methodology.
Introduction to TI’s rad hard Space Products
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2016年 6月 28日
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03:30
Get to know the industry’s largest portfolio of rad hard products and design resources for space flight.