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Developing the SAR reference input model
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所要時間：:
2018年 9月 10日
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18:55
This section shows how to configure all the different components in the model to verify the ADC reference input settling performance.
Rohde & Schwarz: Demystifying 5G - Testing the true performance of ADCs
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2018年 8月 29日
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05:28
Get the ideal combination for high-resolution ADC/DAC testing with the R&S SMA100B RF and microwave analog signal generator from Rohde & Schwarz.
Rohde & Schwarz: Demystifying 5G – Wideband noise and its impact on testing the performance of ADCs
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2018年 8月 29日
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03:39
This video focuses on wideband noise and its impact on the ADC performance.
Rohde & Schwarz: Demystifying 5G - Testing a 5G IF transceiver
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2018年 8月 29日
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06:34
The video explains the benefits of direct RF sampling for 5G systems, and tests a discrete transceiver for 5G NR based on the DAC38RF82 and the ADC12DJ3200.
Microsemi RTG4 FPGA with Texas Instruments ADC12DJ3200
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2018年 8月 23日
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14:59
This video demonstrates connecting the Microsemi RTG4 FPGA development kit with the ADC12DJ3200EVM using the SERDES protocol JEDEC JESD204B.
Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 3
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2018年 7月 25日
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11:22
Learn about the high channel count clocking solution.
Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 2
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2018年 7月 25日
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09:56
Learn about the JESD204B compliant high speed multichannel synchronized clocking architecture
How to synchronize high speed multi-channel clocks?
This training explains how to synchronize high speed multi-channel clocks used in high-speed end equipment with multi-channel transceiver system.
Precision DACs (<=10MSPS) – Learning center
The Precision DAC Learning Center is a collection of technical content that will help guide you through the precision DAC design process.
Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 1
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2018年 7月 17日
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07:50
Learn about the high speed multi-channel clocking requirements and challenges.
Power distribution for SoC and FPGA applications
In this training series, we examine the power requirements of SoC and FPGA devices and discuss the optimal approach to powering them for specific use cases.
Part V: Pre-Compliance EMC Tested Binary Input Module, TI design TIDA-00847
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2018年 6月 4日
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06:21
Introduction to Binary input Architecture and details of TIDA-00847 TI design
Wireless Multi-parameter Patient Monitor Demo
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2018年 6月 1日
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04:01
A simple, wearable, wireless, multi-parameter, patient monitor operated using coin-cell battery and supporting raw data over Bluetooth® 5
Signal acquisition system using our high resolution SAR converters
The training describes a design for CW Doppler signal conditioning for an ultrasound machine that utilizes our 20-bit SAR ADC.
Overview of reference drive topologies
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2018年 5月 11日
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14:27
This video introduces the reference buffer and other reference drive topologies, and how they impact ADC performance.
Voltage reference overview for ADC
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2018年 5月 11日
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12:13
This section covers reference specifications, to gain a deeper understanding of how the voltage reference impacts the performance of the ADC system.
Introduction—Why isolation is necessary for using shunts in poly-phase systems
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2018年 5月 7日
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04:31
This module covers why isolation is necessary for using shunts in poly-phase systems.
Types of noise in ADCs
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2018年 5月 1日
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15:45
This video explains the difference between quantization noise and thermal noise.
External EOS protection devices
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2018年 5月 1日
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10:33
This presentation covers a short review of external devices that can be used to protect data converters from electrical overstress.
Import diode's PSpice model into TINA
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2018年 5月 1日
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03:56
In this presentation we will cover a method for importing a SPICE netlist into TINA.