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Module 2: Standard specifications and extensions in OpenVX
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所要時間：:
2020年 8月 9日
所要時間：:
05:25
In this training, we discuss the official OpenVX specification and extensions supported by TI.
Module 2: How to maximize performance and minimize development cost with OpenVX
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所要時間：:
2020年 8月 9日
所要時間：:
04:54
In this training, you'll learn how to maximize performance while minimizing development cost using OpenVX.
Module 2: How to gain application efficiencies developing in OpenVX
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2020年 8月 9日
所要時間：:
07:12
Learn to make your applications perform more efficiently in OpenVX.
Module 2: These tools make OpenVX development a breeze
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所要時間：:
2020年 8月 9日
所要時間：:
05:01
Learn about tools and programs to help you accelerate your development in OpenVX.
Module 1: See how simple it is to develop with OpenVX
日付:
所要時間：:
2020年 8月 9日
所要時間：:
03:55
OpenVX has a simple programming model, which we demonstrate walking through an application example.
Module 1: How OpenVX compares to other popular compute frameworks
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所要時間：:
2020年 8月 9日
所要時間：:
07:05
See how OpenVX compares to and contrasts with other popular compute frameworks like OpenCV.
OpenVX framework for heterogeneous compute on Jacinto™ 7 processors
This two-part series introduces the OpenVX framework for heterogeneous compute on our Jacinto 7 processors.
Module 1: An overview of the OpenVX framework for heterogeneous compute
日付:
所要時間：:
2020年 8月 7日
所要時間：:
06:48
In this training, we introduce the OpenVX framework on Jacinto 7 processors.
Give your inventory scalability and flexibility with the Sitara™ processors
日付:
所要時間：:
2020年 5月 29日
所要時間：:
02:20
Watch this video for a single-chip solution to build connected devices that support multiple industrial Ethernet protocols.
Multi-camera ADAS demo powered by Jacinto processors
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所要時間：:
2020年 3月 20日
所要時間：:
00:54
This demo shows a single Jacinto TDA4VM processor powering eight, 2 MP cameras that could be used, for example, in a surround view ADAS application.
How to diagnose and debug embedded software program crashes using TI’s ROV debugger
日付:
所要時間：:
2020年 3月 17日
所要時間：:
36:00
This video describes how to detect several common causes of embedded software, primarily those associated with memory corruption.
Output Capacitor Selection Using a Target Impedance Approach
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所要時間：:
2020年 2月 10日
所要時間：:
08:24
Study two techniques for selecting output capacitance to meet transient specs
DC Load Lines: How They Can Benefit Your Next Design
日付:
所要時間：:
2020年 2月 10日
所要時間：:
05:04
Get top of the line performance out of your regulator by adding a DC Load Line
Understanding Transient Response In the Time and Frequency Domain
日付:
所要時間：:
2020年 2月 10日
所要時間：:
05:10
Dive into how a regulator's transient response looks in both time and frequency
Jacinto 7 processors: Overview of SoC subsystems and features
日付:
所要時間：:
2019年 12月 30日
所要時間：:
17:08
An introduction to Jacinto™ 7 processors, including device architecture, key features and subsystems
Jacinto 7 processors: heterogeneous processing cores
日付:
所要時間：:
2019年 12月 30日
所要時間：:
08:08
An introduction to Jacinto™ 7 processing cores and the features and benefits they provide.
Voltage regulator design and optimization for high-current, fast-slew-rate load transients
Learn techniques to design your regulator to high-performance transient specifications.
KeyStone™ architecture
This video series provides an introduction to the functional architecture of the C66x DSP + ARM® embedded processors.
KeyStone™ memory and transport
This section provides information about the memory and transport architectures of the C66x DSP + ARM® embedded processors.
KeyStone™ external interfaces
This section provides training on the external interfaces of the C66x DSP + ARM® embedded processors.