The videos in this series will discuss distributed vs. centralized clock tree, synchronous vs. free-running designs and other selection criteria requirements to help narrow down a clock tree solution. We will discuss other design considerations including frequency planning, spurious and EMI noise reduction techniques, system clock optimization/tuning and clocking for JESD204 B/C systems.

TI Precision Labs (TIPL) is the most comprehensive online classroom for analog signal chain designers. From foundational knowledge to advanced concepts, our logical, sequenced and comprehensive teaching approach is both intuitive and practical. The training series, which includes videos and downloadable reference materials, will deepen the technical expertise of experienced engineers and accelerate the development of those early in their career.

The JESD204B video blog series explores the basic concepts related to the JESD204B SerDes standard in relation to High Speed Data Converter products.

This series explores the new realm of RF sampling converters for use in high frequency, large bandwidth systems.

This series explores advanced topics related to the JESD204B SerDes standard associated with extending the link length and multi-device synchronization.

This series covers general updates on Texas Instruments' high-speed signal chain portfolio.