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Filters in use:
Filters in use:
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並べ替え:
Control of PWM converters
This module will introduce control of pulse-width modulated (PWM) converters.
Linear regulators (LDOs)
日付:
所要時間::
2021年 3月 27日
所要時間::
14:35
This lecture introduces linear regulators, which are a simple, inexpensive way to regulate an output voltage.
Switching converters
日付:
所要時間::
2021年 3月 27日
所要時間::
06:50
This lecture introduces switching converters, which uses a switching element to transform the incoming power supply into a pulsed voltage.
Challenges in modeling switch-mode converters
日付:
所要時間::
2021年 3月 27日
所要時間::
09:28
The lecture will discuss why modeling switch-mode power converters for the purpose of designing controllers is so difficult.
Averaged models
日付:
所要時間::
2021年 3月 27日
所要時間::
12:46
This lecture will discuss the first step in developing an LTI model for a power converter, and the first step is known as averaging.
Linearized models
日付:
所要時間::
2021年 3月 27日
所要時間::
15:01
This lecture will discuss linearizing the average model.
Lab: Measuring loop gain of power converters
日付:
所要時間::
2021年 3月 27日
所要時間::
03:56
This lab will discuss how to measure the loop gain of a power converter and see if it changes with different operating conditions.
Small-signal modeling of PWM converters
This module will introduce small-signal modeling of pulse width modulation (PWM) converters.
Parasitic capacitance
日付:
所要時間::
2021年 3月 26日
所要時間::
22:22
This lecture will discuss parasitic capacitance, the problems it can cause and how to mitigate it.
Parasitic inductance
日付:
所要時間::
2021年 3月 26日
所要時間::
23:09
This lecture will discuss parasitic inductance that comes from the layout of power converters and what it does to the power converter system.
Layout priorities
日付:
所要時間::
2021年 3月 26日
所要時間::
15:52
This lecture will discuss prioritizing different aspects of layout to achieve a good result in a reasonable amount of time.
Gate loop layout
日付:
所要時間::
2021年 3月 26日
所要時間::
18:37
This lecture will discuss laying out gating loops to minimize inductance and get high performance.
Switching loop layout
日付:
所要時間::
2021年 3月 26日
所要時間::
17:02
This lecture will discuss how to design switching loop.
Voltage probing, aka ditch the alligator clip
日付:
所要時間::
2021年 3月 26日
所要時間::
11:56
This lecture will discuss doing good voltage probing when talking about high-frequency signals.
Lab: High-frequency voltage probing
日付:
所要時間::
2021年 3月 26日
所要時間::
04:09
This lab will discuss the impact of low parasitic and high parasitic voltage measurements and how to make good test points.
Lab: Measurement loops and voltage sensing
日付:
所要時間::
2021年 3月 26日
所要時間::
02:51
This lab will demonstrate the parasitic coupling between different loops in a power converter can affect its operation or the measurements that you take.
Layout and parasitics in power converters
This module will introduce layout and parasitics in power converters.
Core saturation
日付:
所要時間::
2021年 3月 26日
所要時間::
16:20
This lecture will discuss core saturation, which is one of the main limitations in designing a magnetic component.
Core loss
日付:
所要時間::
2021年 3月 26日
所要時間::
15:03
This lecture will discuss core loss or real energy losses that occur within a magnetic core.
Does permeability matter?
日付:
所要時間::
2021年 3月 26日
所要時間::
14:06
This lecture will discuss if the permeability of a core material really matters.