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1.4 KeyStone C66x DSP CorePac Overview

Watch the next video in the series:

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Date: January 1, 2012

This module discusses how high performance can be achieved within each C66x DSP core. Topics include C66x DSP CorePac architecture, Single Instruction Multiple Data (SIMD), memory access, and software pipelining.

Click here to view the module (31 minutes)

Related courses and events

KeyStone Turbo Encoder Co-Processor (TCP3E)
Date:
November 1, 2010
KeyStone I training: C66x CorePac overview - achieving high performance
Date:
October 9, 2010
TI-RTOS Workshop Series 4 of 10 - TI-RTOS Configuration
Date:
April 30, 2015
Multicore Software Development Kit (MCSDK) for KeyStone Devices
Date:
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KeyStone I training: fast fourier transform coprocessor (FFTC)
Date:
November 9, 2010

This course is also a part of the following series

66AK2Gx Processor Training Series
Date: April 29, 2016

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