1.4 KeyStone I training: C66x CorePac overview - achieving high performance
1.3 KeyStone II DSP+ARM SoC Architecture Overview">
1.5 KeyStone I training: instruction set architecture (ISA)">
Description
October 9, 2010
CorePac: Achieving High Performance discusses how high performance can be achieved within each DSP core. Topics include CorePac architecture, Single Instruction Multiple Data (SIMD), memory access, and software pipelining.
