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1.3 KeyStone II DSP+ARM SoC Architecture Overview

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Date: November 1, 2012

This module provides a high-level view of the device architecture, including the C66x DSP and ARM Cortex-A15 processors, memory and transport topologies, networking and interface enhancements, as well as power saving and debug features for KeyStone II DSP+ARM multicore devices.

Click here to view the module (26 minutes)

This course is also a part of the following series

66AK2Gx Processor Training Series
Date: April 29, 2016
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