힌트: 여러 단어는 쉼표로 구분

예: 12/03/2021

예: 12/03/2021

힌트: 여러 단어는 쉼표로 구분

예: 12/03/2021

예: 12/03/2021

정렬 기준:

103 결과

Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 1

날짜:
2018년 7월 17일

기간::
07:50
Learn about the high speed multi-channel clocking requirements and challenges.

How to Select Display SerDes for HMI Systems

날짜:
2018년 5월 8일

기간::
04:19
How to select proper serializer and deserializer for the signal transmission in the relevant applications of human-machine interface (HMI).

Get Your Clocks in Sync for JESD204B Data Converters

날짜:
2017년 9월 6일

기간::
19:17
This video will explore a reference design that shows how to synchronize multiple high-speed JESD204B data converters.

Get Your Clocks in Sync: Hardware Setup

날짜:
2017년 8월 14일

기간::
02:31
This video demonstrates DEV_CLK skew between two clock outputs of the clocking reference design and the analog channel to channel skew between 2 ADC12DJ3200EVMs

Get Your Clocks in Sync: Software Setup

날짜:
2017년 8월 7일

기간::
04:20
This video demonstrates the software setup of the Multi-Channel JESD204B 15 GHz Clocking Reference Design for DSO, Radar and 5G Wireless Testers

How to read an SMD part number

날짜:
2017년 2월 7일

기간::
04:38
Learn how to read a SMD (Standard Microcircuit Drawing) part number.
SEPIC Mode Converters for Automotive LCD Displays Technical Overview

SEPIC Mode Converters for Automotive LCD Displays - Technical Overview

날짜:
2016년 9월 22일

기간::
20:26
Learn the basics of a DC/DC SEPIC converter, its advantages compared to other DC/DC topologies, and how a SEPIC can help you in your Automotive display design.

Wearable displays with our DLP® Pico™ technology

This training discusses wearable display systems and design considerations.

Jump-Start Your Space Design with the TPS7H3301-SP Evaluation Module

날짜:
2016년 7월 8일

기간::
04:58
The TPS7H3301-SP is the first double-data-rate (DDR) memory-termination LDO for space applications.

Understanding TI's Enhanced Products Value and Risk Mitigation

날짜:
2016년 6월 24일

기간::
04:38
TI’s broad portfolio of enhanced products provide ruggedized components in plastic packaging. Learn about the qualification process and more.

ADC32RF45: 1-GHz Bandwidth RF Sampling Solution

날짜:
2016년 5월 15일

기간::
05:04
The ADC32RF45 is a dual channel, 14-bit, 3-GSPS ADC. This video shows how the ADC32RF45 supports 1-GHz signal bandwidths and beyond for next generation systems.

Understanding Clock Jitter Impact to ADC SNR

날짜:
2015년 7월 21일

기간::
02:57
This video discusses the sampling clock phase noise performance and how its performance over frequency offset impacts the GSPS ADC SNR performance.

High-speed signal chain training series

Your portal to relevant training material on high-speed data converters and high-speed amplifiers.

Selecting a JESD204B Subclass

날짜:
2015년 7월 15일

기간::
05:14
This video discusses the three subclass modes in the JESD204B standard.  The pros and cons of operating in each subclass is discussed.

Introduction to the RF Sampling Architecture

날짜:
2015년 6월 29일

기간::
03:21
Introduction to the RF sampling architecture in contrast to traditional direct conversion architectures typically used in existing transceivers.

Why RF Sampling

날짜:
2015년 6월 29일

기간::
03:15
This video specifically addresses the benefits and advantages RF sampling provides that was limited or not possible with existing technology.

RF Sampling: Managing Data Rates

날짜:
2015년 6월 29일

기간::
03:40
RF Sampling requires fast sampling rates, but the input data rates usually cannot keep pace.  The techniques to mitigate those limitations are addressed.

Synchronizing Multiple JESD204B ADCs

날짜:
2015년 6월 11일

기간::
03:04
This video illustrates synchronizing two ADC12J4000 ADCs employing JESD204B interface

How to Optimize Synthetic Aperture Radar (SAR) Design with TI's 66AK2L06 SoC

날짜:
2015년 6월 8일

기간::
04:39
Optimize Synthetic Aperture Radar, or SAR, with TI’s integrated 66AK2L06 system-on-a-chip. The FPGA alternative is a KeyStone-based device with a JESD204B inte
103 결과
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