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1.5 Linear regulator fundamentals - PMOS
Hello. I'm Alan Martin, and welcome to our topic on linear regulator fundamentals. This module will be discussing PMOS pass elements as the pass transistor inside a linear regulator. Of course, all linear regulators appear as in this diagram. There's a pass transistor controlled by an error amplifier. The inputs of the error amplifier are an internal voltage reference and a feedback divider that is sampling VOUT. That resisted divider can either be internal to the linear regulator in the case of fixed linear regulators, or external to the linear regulator in the case of adjustable regulators. In this particular topology, a p-channel FET is the pass element for the linear regulator control section. And it is driven by an error amplifier that is driving the gate voltage relative to VIN of the particular device. Dropout voltage ultimately is set by the RDS-ON of the internal mOSFET One advantage of the P-FET in this topology is that the ground current required to drive Q1, the pass element, is extremely small. And in fact, that ground current, as we'll show, is independent of the actual load. So here we are driving the PMOS LDO pass element. And you can see that the VGS requirement out of the control amplifier is the primary variable in this type of approach. One particular limitation is that the output voltage is limited by the internal characteristics of the p-channel FET. And ultimately the VGS characteristics of the p-channel FET limit both the input voltage and the minimum output voltage that the device can be operated at. Let's look at the gate drive requirement in the low load current case. In this case, we're providing 50 milliamps of output current, so a relatively low load. This application is a 1.8-volt output configuration. And you'll see that the VGS requirement on the gate-to-source of the pass element is only one volt. In this configuration, the dropout voltage is astonishing. It's only about five millivolts from input to output. So you can see the attraction for trying to configure this particular LDO in this application. If we increase the output current to three amps, the dropout voltage has increased slightly. It's only 50 millivolts in this case. But the VGS is 1.5 volts. So we're really nearing the limitations of what you can do with this kind of a p-channel pass element. But one of the advantages is that this can be built in low-voltage CMOS type processes. And as a result, they're quite inexpensive to manufacture. In summary, the PMOS LDO has the following characteristics. The input voltage has to be higher than the output voltage based on the load current and the On Resistance of the pass element. Well, this requires that the output voltage be higher than the VGS requirements of the pass element, as well. So for very low output voltages, you may be unable to apply a p-channel device. Also, because it is in a common source configuration for the MOSFET, and the drain is what presents the output voltage to the load, then the output capacitor value and its ESR ratings are quite critical if you're to maintain stability. Keep in mind that to achieve similar RDS performance with a PMOS transistor requires a larger die area than an NMOS device. So as a result, the larger die area will affect pricing. It might affect package size, and it may also influence performance. But the advantage is that, with a p-channel device, you're pulling the gate toward ground, and you don't result in situations where you need an external bias supply, as you might require with an NMOS pass element. Thank you for joining us on this topic.
Watch the previous video in the series:
Linear regulator fundamentals - NMOS
Details
Date:
February 25, 2013
This presentation provides an overview of PMOS circuits.
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