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LMK03328 ultra low jitter clock generator step by step design-in process

This 3-part video series outlines the design process for the LMK03328 ultra-low-jitter clock generator.  The series covers the WEBENCH Clock Architect design and simulation process, using the TICS Pro EVM GUI software with WEBENCH design report to help configure the LMK03328 EVM, frequency planning techniques, and using TICS Pro to program multiple startup profiles to the device EEPROM. 

A networking switch clocking example is discussed through the video series to highlight key features and benefits of the LMK03328 Dual PLL clock generator, such as ultra-low phase noise/jitter to improve system performance/margin, EEPROM pin modes to support multiple startup profiles and system validation testing, and flexible frequency planning and frequency margining capabilities.

This design process is also applicable to the LMK03318 (Single PLL version of the LMK03328).

1. LMK03328 Ultra Low Jitter Clock Generator Design Process

# Title Duration
1.1 LMK03328 WEBENCH Clock Architect Design Tutorial
WEBENCH Clock Architect design and simulation process for the LMK03328, including clock design entry and solution, PLL loop filter and clock phase noise...
07:53
1.2 LMK03328 EVM Setup and Programming with TICS Pro GUI
EVM setup and programming using TICS Pro GUI with WEBENCH clock design report to configure and program the device.  The video also covers frequency planning...
08:50
1.3 LMK03328 Frequency Margining and EEPROM programming with TICS Pro GUI
LMK03328 frequency margining example for generating multiple frequency plan configurations (nominal, margin high, and margin low) and programming these...
04:41
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