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SPI JTAG Level translation using AXC4T774EVM
Hello. Today I'm going to talk about using the SN74AXC4T774EVM device to implement low voltage level translation that can be used in common [INAUDIBLE]. The SN74AXC4T774EVM evaluation module will be used to [INAUDIBLE] the implementation of SPI interface. The new AXC family of devices features multiple key advantages. This device family is targeted at the new class of ultra-low voltage processors coming to the market. This will be an industry first for a translation device to support down to 0.65 volts. [INAUDIBLE] glitch-free performance without any specific poverty sequencing requirements. Operating temperature support of up 125 degrees Celsius meets most end equipments. Data rates of up to 380 Mbps enables customers to achieve greater data transfer rates from their design while supporting lower voltages. Small package options will enable customers to achieve bone density needed for aggressive form factors. Compliance to JEDEC standards assures interoperability across interface standards. The new AXC family of devices will have much lower power dissipation. For example, the one bit AXC1T45 has up to 60% lower dissipation than competing solutions. The combination of these benefits results in the AXC family being the best in class for the translation solution in the market today. The AXC4T774 is a 4-bit direction-controlled voltage translator which has all the characteristics of the AXC family, as discussed previously. The unique feature of the device is that it provides individual direction control for each of its four channels during which it can support most of the push/pull interfaces, such as the SPI, JTAG, I2S, among others. If either of the supplies is at ground, the I/Os are placed in high impedance mode, resulting in system power savings due to the VCC isolation feature. This device supports Ioff partial-power-down mode, which prevents current back flow into VCC by disabling the I/Os when either of the supplies is at ground. The device comes in two package variants-- the [INAUDIBLE] TSSOP PW package and the space-saving 4.7 millimeter squared micro QFN RSV package. In the block diagram to the right, SPI voltage translation between an FPGA at 0.8 volts and MCU at 3.3 volts using the AXC4T774 as shown. An evaluation module of the AXC4T774 can be used to set up the SPI translation. Let's do a quick review of the EVM schematic and the board. The schematic shows the RSV package at the top of the EVM and the PW package at the bottom. The 100 mil headers interfaced with each of the device spins while the other side of the header is connected to ground for easier configuration of the control inputs and the data I/O pins. The RSV package has an additional pair of edge-mounted SMB connectors for high-speed interface. The full direction control inputs and the output enable have the option to be connected to either ground or [INAUDIBLE] through the pullup resistors. We can use the EVM to implement SPI level translation using the RSV package as an example here, between the processor I/Os operating at 0.8 volts and peripheral I/Os operating at 3.3 volts. First connect the device ground to system ground. Connect the processors 0.8 volts supplied to VCCA header pin. Connect the peripheral I/Os 3.3 volts supplied to the VCC [INAUDIBLE]. As the AXC family is designed to work without any specific power sequencing requirement, any power supply can be ramped up in any order. The EVM is pre-configured to work for the SPI RJ tag interface. And hence the signal flow is from A to B for the first three channels and B to a for the fourth channel. For more information on the AXC4T774, please visit the product folder page on TI.com. And thank you for watching.
Details
Date:
July 5, 2019
This video gives an overview of the AXC family of devices and focuses on level translation using the SN74AXC4T774EVM.
Additional Information
Explore SN74AXC4T774 EVM
Low voltage translation for SPI, JTAG, UART, RGMII
SN74AXC4T774
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