KeyStone™ architecture

This section provides an introduction to the functional architecture of the C66x DSP + ARM® embedded processors, as well as the DSP and ARM cores and the Instruction Set Architecture (ISA).

Additional information

Learn more about the KeyStone™ family of DSP and DSP + ARM processors

1KeyStone™ architecture (3)

This video series provides an introduction to the functional architecture of the C66x DSP + ARM® embedded processors.

10:26

1.1 KeyStone I Training: C665x SoC Overview

31:03

1.2 KeyStone I training: C66x CorePac overview - achieving high performance

30:57

1.3 KeyStone I training: instruction set architecture (ISA)

3KeyStone™ external interfaces (4)

This section provides training on the external interfaces of the C66x DSP + ARM® embedded processors.

04:20

3.1 KeyStone I training: network coprocessor (NETCP) overview

26:36

3.2 KeyStone I training: NETCP - packet accelerator (PA)

15:45

3.3 KeyStone I training: NETCP - security accelerator (SA)

22:05

3.4 KeyStone I training: I/O interfaces

4KeyStone™ wireless accelerators and co-processors (3)

This section provides an overview of the wireless accelerators and co-processors on C66x DSP + ARM® embedded processors.

01:17:03

5KeyStone™ software and tools (4)

This section introduces various software and tools on C66x DSP + ARM® embedded processors.

17:42

KeyStone™ architecture

Additional information

1KeyStone™ architecture (3)

1.1 KeyStone I Training: C665x SoC Overview

1.2 KeyStone I training: C66x CorePac overview - achieving high performance

1.3 KeyStone I training: instruction set architecture (ISA)

2KeyStone™ memory and transport (5)

2.1 KeyStone I training: memory and cache

2.2 KeyStone I training: multicore navigator overview

2.3 KeyStone I training: multicore navigator - queue manager subsystem (QMSS)

2.4 KeyStone I training: multicore navigator - packet DMA (PKTDMA)

2.5 KeyStone I training: introduction to interprocessor communication (IPC)

3KeyStone™ external interfaces (4)

3.1 KeyStone I training: network coprocessor (NETCP) overview

3.2 KeyStone I training: NETCP - packet accelerator (PA)

3.3 KeyStone I training: NETCP - security accelerator (SA)

3.4 KeyStone I training: I/O interfaces

4KeyStone™ wireless accelerators and co-processors (3)

4.1 KeyStone I training: antenna Interface V2 (AIF2)

4.2 KeyStone I training: fast fourier transform coprocessor (FFTC)

4.3 KeyStone I training: turbo decoder co-processor (TCP3D)

5KeyStone™ software and tools (4)

5.1 KeyStone I training: multicore software development kit (MCSDK) overview

5.2 KeyStone I training: bootloader overview

5.3 KeyStone I training: power management

5.4 KeyStone I training: debug overview

6KeyStone™ demonstrations (4)

6.1 Restoring Factory Default Images on KeyStone II Platforms

6.2 Demonstrating U-Boot from SPI/QSPI for 66AK2G

6.3 Demonstrating Voice Preprocessing on the EVMK2G

6.4 Getting Started with the EVMK2EX Development Board for 66AK2Ex and AM5K2Ex Processors

7Processor SDK for our embedded processors (5)

7.1 Introduction to the Processor SDK Training Series

7.2 Introduction to Processor SDK RTOS Part 1

7.3 Introduction to Processor SDK RTOS Part 2

7.4 Application Development Using Processor SDK RTOS

7.5 Setting Up and Testing Processor SDK RTOS Device Drivers

KeyStone™ architecture

Additional information

1KeyStone™ architecture (3)

2KeyStone™ memory and transport (5)

3KeyStone™ external interfaces (4)

4KeyStone™ wireless accelerators and co-processors (3)

5KeyStone™ software and tools (4)

6KeyStone™ demonstrations (4)

7Processor SDK for our embedded processors (5)

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