PCIe

Email

PCIe layout guidelines

Description

December 22, 2021
In this series we are going to discuss board layout recommendations for the peripheral component interconnect express or PCle.  PCIe is a high-performance interconnect that enables high bandwidth, scalable, error detection, and hot-swap functionality across multiple clock boundaries. To accommodate high bandwidth and scalability, multiple traces carrying high-speed data at 16Gbps or higher are used.  These high-speed lanes require special considering when designing a PCB layout.   

Download webinar slides

Additional information

arrow-topclosedeletedownloadmenusearchsortingArrowszoom-inzoom-out arrow-downarrow-uparrowCircle-leftarrowCircle-rightblockDiagramcalculatorcalendarchatBubble-doublechatBubble-personchatBubble-singlecheckmark-circlechevron-downchevron-leftchevron-rightchevron-upchipclipboardclose-circlecrossReferencedashdocument-genericdocument-pdfAcrobatdocument-webevaluationModuleglobehistoryClockinfo-circlelistlockmailmyTIonlineDataSheetpersonphonequestion-circlereferenceDesignshoppingCartstartoolsvideoswarningwiki