Sitara™ AM57x Processors Training Series

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1.7 Sitara™ Processors: Running TI-RTOS on the ARM Cortex™-M4 Processor

Description

October 21, 2016

This module provides an introduction to the dual-core ARM Cortex-M4 Image Processing Unit (IPU) Subsystem, including the memory map, cache maintenance and control using UNICACHE and MMU, and bit banding. It also provides an overview of how to create, load, and run applications on the Cortex-M4 and provides an IVA-HD application use case example.

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