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222 Results
 Name * thumb-_developing_the_sar_reference_input_model.jpg Alt Text

Developing the SAR Reference Input Model

Date:
September 10, 2018

Duration:
18:55
This section shows how to configure all the different components in the model to verify the ADC reference input settling performance.

Rohde & Schwarz: Demystifying 5G - Testing the true performance of ADCs

Date:
August 29, 2018

Duration:
05:28
Get the ideal combination for high-resolution ADC/DAC testing with the R&S SMA100B RF and microwave analog signal generator from Rohde & Schwarz.

Rohde & Schwarz: Demystifying 5G - Wideband noise and its impact on testing the true performance of ADCs

Date:
August 29, 2018

Duration:
03:39
This video focuses on wideband noise and its impact on the ADC performance.

Rohde & Schwarz: Demystifying 5G - Testing a 5G IF transceiver

Date:
August 29, 2018

Duration:
06:34
The video explains the benefits of direct RF sampling for 5G systems, and tests a discrete transceiver for 5G NR based on the DAC38RF82 and the ADC12DJ3200.

Microsemi RTG4 FPGA with Texas Instruments ADC12DJ3200

Date:
August 23, 2018

Duration:
14:59
This video demonstrates connecting the Microsemi RTG4 FPGA development kit with the ADC12DJ3200EVM using the SERDES protocol JEDEC JESD204B.

Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 3

Date:
July 25, 2018

Duration:
11:22
Learn about the high channel count clocking solution.

Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 2

Date:
July 25, 2018

Duration:
09:56
Learn about the JESD204B compliant high speed multichannel synchronized clocking architecture

How to synchronize high speed multi-channel clocks?

Modern high speed end equipment's like oscilloscope, 5G wireless communication tester and RADAR requires multichannel transceiver system. The biggest challenge is to provide the high frequency, low phase noise, multiple synchronized clocks to each transceiver's data converters and local oscillator. This training will explain how to synchronize the high speed multi-channel clocks and expand for high channel count clocks requirement.

Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 1

Date:
July 17, 2018

Duration:
07:50
Learn about the high speed multi-channel clocking requirements and challenges.

Part V: Pre-Compliance EMC Tested Binary Input Module, TI design TIDA-00847

Date:
June 4, 2018

Duration:
06:21
Introduction to Binary input Architecture and details of TIDA-00847 TI design

Signal Acquisition system using TI’s High Resolution SAR Converters

The report illustrates a differentially driven signal fed into TI’s 20 bit SAR ADC. This results in raw data available for data processing. This has zero latency and high linearity.

This TI design illustrate the CW Doppler signal conditioning for an ultrasound machine. The input signal bandwidth up to 100KHz and 128 differential signals from AFEs are summed together in a differential high speed amplifier and digitized with TI SAR ADC.

This presentation also addresses :

An adaptive circuit for adjusting the cut off frequency of anti-aliasing circuit in our explanations.

Overview of Reference Drive Topologies

Date:
May 11, 2018

Duration:
14:27
This video introduces the reference buffer and other reference drive topologies, and how they impact ADC performance.

Voltage Reference Overview for ADC

Date:
May 11, 2018

Duration:
12:13
This section covers reference specifications, to gain a deeper understanding of how the voltage reference impacts the performance of the ADC system.

Polyphase current measurement with isolated shunt sensors: Introduction—Why isolation is necessary for using shunts in poly-phase systems

Date:
May 7, 2018

Duration:
04:31
This module covers why isolation is necessary for using shunts in poly-phase systems.
Types of noise in ADCs

Types of noise in ADCs

Date:
May 1, 2018

Duration:
15:45
This video explains the difference between quantization noise and thermal noise.
Import Diode's spice model into TINA

Import Diode's PSpice Model into TINA

Date:
May 1, 2018

Duration:
03:56
In this presentation we will cover a method for importing a SPICE netlist into TINA.
Protecting low voltage ADC

Protecting Low Voltage ADC from High Voltage Amp

Date:
May 1, 2018

Duration:
23:28
This video covers component selection to protect low voltage data converters driven by high voltage amplifiers.
Protecting ADC with TVS Diode

Protecting ADC with TVS Diode

Date:
May 1, 2018

Duration:
19:22
This video shows how to select TVS diodes, and current limiting resistors to protect ADC.
Protecting ADCS with TVS Diode, improved solution

Protecting ADC with TVS Diode – Improved Solution

Date:
May 1, 2018

Duration:
14:43
This presentation shows how a PTC-Fuse can be added to improve the performance of a TVS diode protection circuit.
Introduction to noise in ADC systems

Introduction to noise in ADC systems

Date:
May 1, 2018

Duration:
13:01
Covers what noise is, where it comes from, and why it’s important when designing ADC systems.
222 Results
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