This section analyzes the link between the 953 and 954 and establishes how to identify the health and operation of the link. Since the link between the 953-954 is the most fundamental link used to communicate between devices, it is often checked first.
Specifically, this section discusses: Back Channel configuration, Built in Self Test (BIST), Adaptive Equalization (AEQ), and Channel Monitor Loop (CMLOUT)
This section discusses what frame synchronization (FrameSync) is and how to configure in on the 953 and 954 and how CSI2 data is transferred across the link from the 954 to the ISP/SoC
Specifically, this section discusses: Frame Synchronization (FrameSync), Controlling 953 GPIOs locally and remotely via I2C, Unsynchronized and synchronized sensors, Internal and External Frame Sync, Port Forwarding, Accessing Indirect Registers, and Pattern Generation on 953 & 954
This section discusses how design a 953/954 using Power over Coax (PoC), and various hardware checks and concepts that need to be considered when analyzing a 953/954 system.
Specifically, this section discusses: Power Over Coax (PoC), AC Coupling Capacitors, PoC Inductors, Typical PoC Schematic, Critical Signal Routing, I2C Pullups, Loop Filter Capacitors on 953, Insertion Loss, Return Loss, and Time Domain Reflection (TDR) measurements.
These introduction videos describe the evolution of FPD-Link product families, and introduction to FPD-Link III SerDes for use in Infotainment and ADAS applications.
This video series provides an overview of diagnostic capabilities of FPD-Link III and basic tips to simplify troubleshooting.
This video series describes the key parameters used in the FPD-Link high-speed serial link consisting of the serializer, transmission medium and the de-serializer.
This video series describes the concept, design and evaluation of PoC (power over coax) commonly used in ADAS sub-systems.
This video series describes the interfaces to sensor or video IO's of a graphics processor.