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98 Results
Implementing automotive displays with SerDes daisy chaining & local dimming backlight architecture

Implementing automotive displays with SerDes daisy chaining & local dimming backlight architecture

Date:
August 28, 2020

Duration:
38:52
Implementing automotive displays with SerDes daisy chaining & local dimming backlight architecture
Automotive in-cabin sensing with 60-GHz single-chip radar

Automotive in-cabin sensing with 60-GHz single-chip radar

Date:
August 24, 2020

Duration:
45:29
Automotive in-cabin sensing with 60-GHz single-chip radar
FPD-Link High Speed Design and Channel Requirements

FPD-Link High Speed Design and Channel Requirements

Date:
August 20, 2020

Duration:
47:03
FPD-Link High Speed Design and Channel Requirements
dlp, transparent window display, holographic digital cluster, automotive, dlp auto, dlp5534-q1

CERES holographic digital windscreen cluster demo

Date:
January 22, 2020

Duration:
01:33
The combination of a CERES holographic film and TI DLP® Auto projector creates a high resolution transparent window display.
dlp, dlp auto, dlp transparent window display, autonomous cars, dlp5534-q1

Take a closer look at the TI DLP Auto transparent window display demo

Date:
January 8, 2020

Duration:
01:57
The TI DLP® Auto transparent window display demo showcases static and moving images displayed on any window in an auto as well as capacitive touch interaction.

Jacinto 7 evaluation module accelerates next-generation ADAS and Gateway application development

Date:
January 2, 2020

Duration:
03:23
Watch this video to discover how to evaluate TDA4x and DRA82x processors in next-generation ADAS and Gateway applications.
Creating ADAS applications with Processor SDK Automotive

Processor SDK for Jacinto 7: Creating ADAS applications

Date:
December 30, 2019

Duration:
14:18
How to create an ADAS application on the Jacinto™ 7 TDA4VMx evaluation module using Processor SDK

Processor SDK for Jacinto 7: getting started

Date:
December 30, 2019

Duration:
11:24
How to get started building and running demonstrations on the Processor SDK for Jacinto™ 7 processors
Jacinto 7 device overview

Jacinto 7 processors: Overview of SoC subsystems and features

Date:
December 30, 2019

Duration:
17:08
An introduction to Jacinto™ 7 processors, including device architecture, key features and subsystems
Jacinto 7 processors: heterogeneous processing cores

Jacinto 7 processors: heterogeneous processing cores

Date:
December 30, 2019

Duration:
08:08
An introduction to Jacinto™ 7 processing cores and the features and benefits they provide.
Jacinto 7 processors: application-specific hardware accelerators

Jacinto 7 processors: application-specific hardware accelerators

Date:
December 30, 2019

Duration:
07:32
An introduction to Jacinto™ 7 hardware accelerators and the features and benefits they provide.
Jacinto 7 processors: virtualization, security, and power

Jacinto 7 processors: virtualization, security, and power

Date:
December 30, 2019

Duration:
07:55
An introduction to virtualization, security, and power management on Jacinto™ 7 processors.
Enabling thermal safety for automotive infotainment and cluster systems - Termperature sensors

How to enable thermal safety for automotive infotainment and cluster systems

Date:
October 11, 2019

Duration:
09:04
How to enable thermal safety for automotive infotainment and cluster systems

DS90UB953/954 System Design & Operation: Overview

This introduction video will give the background on FPD-Link III devices, such as the DS90UB953-Q1/ DS90UB954-Q1; the device's role within Advanced Driver Assist Systems (ADAS) in the automotive industry; and explain their broad appeal to engineers of all experience levels. This is fundamental to diving deeper into a 953/954 system, as well as, the links within the system.

DS90UB953/954 System Design & Operation: Typical Customer Issues

This section frames the design and operation video series by showing why it is important to contextualize customer problems in terms of the links between the devices. 

Specifically, this section will discuss: issues with initializing the camera and issues with reading the incorrect serializer ID from the deserializer.

DS90UB953/954 System Design & Operation: Basic Design Rules

Understanding what hardware and software settings are important is critical to establishing a foundation for the 953/954 system. These settings can occur during or after power up and may need to be changed via software. As a result, these settings are routinely checked and verified before checking any of the other links in the system.

Specifically, this sections discusses: Diagnostics post power up, Mode and IDX Pins, Clocking Modes between the 953/954, Aliasing, I2C Pass Through, Port selection on 954, Analog Launch Pad (ALP), and Successful I2C Communication

DS90UB953/954 System Design & Operation: 953-954 Link Design

This section analyzes the link between the 953 and 954 and establishes how to identify the health and operation of the link. Since the link between the 953-954 is the most fundamental link used to communicate between devices, it is often checked first.

Specifically, this section discusses: Back Channel configuration, Built in Self Test (BIST), Adaptive Equalization (AEQ), and Channel Monitor Loop (CMLOUT)

DS90UB953/954 System Design & Operation: Sensor-953 Link Design

This is the Sensor and 953 Link Design section in DS90UB953/954 System Design & Operation video series. This video discusses how to use the sensor-953 link, as well as, the specific settings that are used with this link.

DS90UB953/954 System Design & Operation: 954-ISP/SoC Link Design

This section discusses what frame synchronization (FrameSync) is and how to configure in on the 953 and 954 and how CSI2 data is transferred across the link from the 954 to the ISP/SoC

Specifically, this section discusses: Frame Synchronization (FrameSync), Controlling 953 GPIOs locally and remotely via I2C, Unsynchronized and synchronized sensors, Internal and External Frame Sync, Port Forwarding, Accessing Indirect Registers, and Pattern Generation on 953 & 954

DS90UB953/954 System Design & Operation: Hardware Design

This section discusses how design a 953/954 using Power over Coax (PoC), and various hardware checks and concepts that need to be considered when analyzing a 953/954 system.

Specifically, this section discusses: Power Over Coax (PoC), AC Coupling Capacitors, PoC Inductors, Typical PoC Schematic, Critical Signal Routing, I2C Pullups, Loop Filter Capacitors on 953, Insertion Loss, Return Loss, and Time Domain Reflection (TDR) measurements.

98 Results
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