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LMK03328 ultra low jitter clock generator step by step design-in process
This 3-part video series outlines the design process for the LMK03328 ultra-low-jitter clock generator. The series covers the WEBENCH Clock Architect design and simulation process, using the TICS Pro EVM GUI software with WEBENCH design report to help configure the
LMK03328 WEBENCH Clock Architect Design Tutorial
Date:
Duration:
January 12, 2017
Duration:
07:53
WEBENCH Clock Architect design and simulation process for the LMK03328, including clock design entry and solution, PLL loop filter and clock phase noise optimiz
LMK03328 EVM Setup and Programming with TICS Pro GUI
Date:
Duration:
January 13, 2017
Duration:
08:50
EVM setup and programming using TICS Pro GUI with WEBENCH clock design report to configure and program the device. The video also covers frequency planning tec
LMK03328 Frequency Margining and EEPROM programming with TICS Pro GUI
Date:
Duration:
January 13, 2017
Duration:
04:41
LMK03328 frequency margining example for generating multiple frequency plan configurations (nominal, margin high, and margin low) and programming these to the E
Webinar - What you need to know about Clock Generators, Buffers and RF Synthesizers
Date:
Duration:
June 27, 2018
Duration:
54:18
Want to learn more about Clock Generators and Buffers ? You're in the right place!