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8 Results

Design Considerations for Robust Interface Between J6 and Car Displays via FPD-Link [Part 3]

Date:
April 21, 2017

Duration:
03:14
Clock cleaners can be incorporated into a system design if jitter issues continue after PCB guidelines and followed and PLL configurations are optimized.
 The TIDA-01021 connected to the ADC12DJ3200EVM and LMX2594EVM.

Get Your Clocks in Sync: Hardware Setup

Date:
August 14, 2017

Duration:
02:31
This video demonstrates: DEV_CLK skew between the two clock outputs of the TIDA-01021 and the analog channel to channel skew between 2x ADC12DJ3200EVMs
Software capture of the TIDA-01021 clocking reference design for DSO, Radar and 5G Wireless Testers

Get Your Clocks in Sync: Software Setup

Date:
August 7, 2017

Duration:
04:20
This video demonstrates the software setup of the Multi-Channel JESD204B 15 GHz Clocking Reference Design for DSO, Radar and 5G Wireless Testers

TI Clock and Timing Solutions

When: June 21, 2018 at 10:30 am
Learn about the industry's best PLL and it's unique features for your next design.

TI Solutions for Clock and Timing

Date:
December 7, 2017

Duration:
16:05
Learn about solutions to common aerospace and defense design challenges to help you simplify designs and improve performance.

TX Signal Chain Implementation for Wide Band and High Frequency Signal Generation

Date:
November 10, 2016

Duration:
13:45
The system design for an arbitrary waveform generator (AWG) and its functional blocks, including a discussion of the AWG amplifier path and design methodology.

Get Your Clocks in Sync

Date:
September 6, 2017

Duration:
19:17
Learn how to synchronize multi-channel high-speed clocks!

Webinar: TI Clock and Timing Solutions

When: June 21, 2018 at 10:30 am
Clock and timing solutions to help you simplify your design and improve performance.
8 Results