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11 Results

Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 3

Date:
July 25, 2018

Duration:
11:22
Learn about the high channel count clocking solution.

Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 2

Date:
July 25, 2018

Duration:
09:56
Learn about the JESD204B compliant high speed multichannel synchronized clocking architecture

Get Your Clocks in Sync for JESD204B Data Converters

Date:
September 6, 2017

Duration:
19:17
This video will explore a reference design that shows how to synchronize multiple high-speed JESD204B data converters.

Get Your Clocks in Sync: Hardware Setup

Date:
August 14, 2017

Duration:
02:31
This video demonstrates DEV_CLK skew between two clock outputs of the clocking reference design and the analog channel to channel skew between 2 ADC12DJ3200EVMs

Get Your Clocks in Sync: Software Setup

Date:
August 7, 2017

Duration:
04:20
This video demonstrates the software setup of the Multi-Channel JESD204B 15 GHz Clocking Reference Design for DSO, Radar and 5G Wireless Testers
LMK03328 Frequency Margining

LMK03328 Frequency Margining and EEPROM programming with TICS Pro GUI

Date:
January 13, 2017

Duration:
04:41
LMK03328 frequency margining example for generating multiple frequency plan configurations (nominal, margin high, and margin low) and programming these to the E
LMK03328EVM setup

LMK03328 EVM Setup and Programming with TICS Pro GUI

Date:
January 13, 2017

Duration:
08:50
EVM setup and programming using TICS Pro GUI with WEBENCH clock design report to configure and program the device.  The video also covers frequency planning tec

システム性能の最適化と設計時間 超低クロック・ジェネレータ LMK03328

Date:
January 13, 2016

Duration:
07:12
今日はTIの最新クロック・ジェネレータLMK03328の性能および機能に関するデモをお見せします。

Optimize System Performance and Design Time with the LMK03328 Ultra-Low-Jitter Clock Generator

Date:
September 28, 2015

Duration:
07:12
Deepa shows us how easy it is to implement the LMK03328 features in your system design.

Utilizing JESD204B interface in low cost applications

Date:
November 8, 2014

Duration:
02:47
Get an overview of the 4-channel, 50-MSPS DEV-ADC34J22 evaluation module. The board features TI's ADC34J22 ADC, LMK04828 jitter cleaner and THS4541 fully diffe

Frequency planning and loop filter design using CDCE62005

Date:
November 1, 2014

Duration:
04:14
Planning and loop filter design is now easy using the latest tools available in the CDCE62005 GUI.
11 Results
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