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システム性能の最適化と設計時間 超低クロック・ジェネレータ LMK03328

Date:
January 13, 2016

Duration:
07:12
今日はTIの最新クロック・ジェネレータLMK03328の性能および機能に関するデモをお見せします。

Utilizing JESD204B interface in low cost applications

Date:
November 8, 2014

Duration:
02:47
Get an overview of the 4-channel, 50-MSPS DEV-ADC34J22 evaluation module. The board features TI's ADC34J22 ADC, LMK04828 jitter cleaner and THS4541 fully diffe

TX Signal Chain Implementation for Wide Band and High Frequency Signal Generation

Date:
November 10, 2016

Duration:
13:45
The system design for an arbitrary waveform generator (AWG) and its functional blocks, including a discussion of the AWG amplifier path and design methodology.
TI's bulk acoustic wave (BAW) clocking technology

TI's Bulk Acoustic Wave Clocking Technology

Date:
February 25, 2019

Duration:
03:02
This video details TI’s Bulk Acoustic Wave (BAW) clocking technology, optimized to improve network performance, reduce BOM and increase immunity to interference

TI's Bulk Acoustic Wave Clocking Technology

Date:
February 22, 2019

Duration:
03:02
This video details TI’s Bulk Acoustic Wave (BAW) clocking technology, optimized to improve network performance, reduce BOM and increase immunity to interference

TI Solutions for Clock and Timing

Date:
December 7, 2017

Duration:
15:08
Learn about solutions to common aerospace and defense design challenges to help you simplify designs and improve performance.

Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 3

Date:
July 25, 2018

Duration:
11:22
Learn about the high channel count clocking solution.

Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 2

Date:
July 25, 2018

Duration:
09:56
Learn about the JESD204B compliant high speed multichannel synchronized clocking architecture

Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 1

Date:
July 17, 2018

Duration:
07:50
Learn about the high speed multi-channel clocking requirements and challenges.

Reduce design risk for Low Earth Orbit satellites and other New Space applications

When: October 8, 2019 2:00 pm
What is NewSpace? What does it mean for satellite design? Explore products that meet quality & reliability requirements for short space flights and LEO designs.

Program Clock Distribution Circuits - ClockPro

Date:
November 8, 2014

Duration:
01:47
Learn how to program TIClock Pro and TI Clock distribution circuits using ClockPro software.

Optimize System Performance and Design Time with the LMK03328 Ultra-Low-Jitter Clock Generator

Date:
September 28, 2015

Duration:
07:12
Deepa shows us how easy it is to implement the LMK03328 features in your system design.

LMK04826/8: JESD204B-compliant clock jitter cleaners

Date:
November 8, 2014

Duration:
10:39
Timothy demonstrates how to use the LMK0482x devices in JESD204B applications and illustrates the benefits of designing with the JESD204B interface.

LMK04800 Clock Jitter Cleaner/Distribution Demo

Date:
November 2, 2014

Duration:
05:23
Alan demonstrates the LMK04800 clock jitter cleaner and distribution family including: * Ultra-Low RMS Jitter Performance using low-cost external crystal
LMK03328 Frequency Margining

LMK03328 Frequency Margining and EEPROM programming with TICS Pro GUI

Date:
January 13, 2017

Duration:
04:41
LMK03328 frequency margining example for generating multiple frequency plan configurations (nominal, margin high, and margin low) and programming these to the E
LMK03328EVM setup

LMK03328 EVM Setup and Programming with TICS Pro GUI

Date:
January 13, 2017

Duration:
08:50
EVM setup and programming using TICS Pro GUI with WEBENCH clock design report to configure and program the device.  The video also covers frequency planning tec

Introduction to TI’s rad hard Space Products

Date:
June 28, 2016

Duration:
03:31
Get to know the industry’s largest portfolio of rad hard products and design resources for space flight.

How to synchronize high speed multi-channel clocks?

Modern high speed end equipment's like oscilloscope, 5G wireless communication tester and RADAR requires multichannel transceiver system. The biggest challenge is to provide the high frequency, low phase noise, multiple synchronized clocks to each transceiver's data converters and local oscillator. This training will explain how to synchronize the high speed multi-channel clocks and expand for high channel count clocks requirement.

Hitless Switching with DPLL Network Clock Synchronizers from TI

Date:
March 27, 2018

Duration:
01:18
Hitless Switching: Watch how our innovative phase cancellation eliminates phase hits in clock applications.

Get Your Clocks in Sync: Software Setup

Date:
August 7, 2017

Duration:
04:20
This video demonstrates the software setup of the Multi-Channel JESD204B 15 GHz Clocking Reference Design for DSO, Radar and 5G Wireless Testers
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