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205 Results

TI Precision Labs

Date:
October 17, 2017

Duration:
05:24
TI Precision Labs is the electronics industry’s first comprehensive online classroom for analog engineers.
THS4551 Fully Differential Amplifer Overview - ADC Driver

THS4551 Fully Differential Amplifier Overview

Date:
August 12, 2016

Duration:
05:17
THS4551 Low Noise, Precision, 150MHz, Fully Differential Amplifier Overview

Three-part JESD204B training series

This three-part training series introduces fundamentals and tips for leveraging the JESD204B serial interface standard, which provides board area, FPGA/ASIC pin-count and deterministic latency improvements over traditional LVDS and CMOS interfaces. TI’s JESD204B ADCs, DACs, clock ICs and development tools enable quick evaluation, design and implementation of designs utilizing the JESD204B interface. Learn more today through this on-demand series.

Jitter vs SNR for High Speed ADCs

The Impact of Jitter on Signal to Noise Ratio (SNR) for High-Speed Analog-to-Digital Converters (ADCs)

Date:
July 31, 2017

Duration:
08:00
Considerations of Clock jitter, the impact on SNR, how to calculate it and minimize noise degradation for High-Speed Analog-to-Digital Converters.

The HART of the Current Loop: Designing SMART Field Transmitters and PLCs with TI's Very First HART Modem

This presentation series covers analog output design and how HART is used in both analog input modules and analog output modules. It also provides information on the HART testing and certification process.

Talk like a Pro - Data Flow

Date:
July 15, 2015

Duration:
03:54
This video illustrates the block diagram of the JESD204B SERDES transceiver.  The function of the individual blocks is described.

Synchronizing Multiple JESD204B ADCs

Date:
June 11, 2015

Duration:
03:04
This video illustrates synchronizing two ADC12J4000 ADCs employing JESD204B interface

Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 3

Date:
July 25, 2018

Duration:
11:22
Learn about the high channel count clocking solution.

Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 2

Date:
July 25, 2018

Duration:
09:56
Learn about the JESD204B compliant high speed multichannel synchronized clocking architecture

Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 1

Date:
July 17, 2018

Duration:
07:50
Learn about the high speed multi-channel clocking requirements and challenges.
Local oscillator and GHz clocks requirements in Radio applications systems with LMX2594.

specifications video 3 of 5: Local oscillator and GHz clocks requirements in Radio applications systems with LMX2594.

Date:
April 29, 2017

Duration:
22:19
This video is the second part on the specifications of a signal source: Spurs and lock time.
Local oscillator and GHz clocks requirements in Radio applications systems with LMX2594.

specifications video 2 of 5: Local oscillator and GHz clocks requirements in Radio applications systems with LMX2594.

Date:
April 29, 2017

Duration:
20:39
This video is the first part on the specifications of a signal source: Phase noise and jitter.

Solving bandwidth limitations with high speed converters

Date:
October 31, 2018

Duration:
13:40
Achieve wider bandwidth, lower latency and higher density with TI's high speed data converters.
Webinar: Solve smart meter design needs

Solve smart meter design needs in metrology, backup power, wireless communications & battery monitoring

Date:
May 10, 2019

Duration:
43:20
Introduction to new reference designs for smart meters

Signal Acquisition system using TI’s High Resolution SAR Converters

The report illustrates a differentially driven signal fed into TI’s 20 bit SAR ADC. This results in raw data available for data processing. This has zero latency and high linearity.

This TI design illustrate the CW Doppler signal conditioning for an ultrasound machine. The input signal bandwidth up to 100KHz and 128 differential signals from AFEs are summed together in a differential high speed amplifier and digitized with TI SAR ADC.

This presentation also addresses :

An adaptive circuit for adjusting the cut off frequency of anti-aliasing circuit in our explanations.

Selection of Key Components (ADC, Signal Conditioning Amplifier) for AC Analog Input Module (AIM)

Date:
April 15, 2017

Duration:
12:30
Understand some of the key criteria for selection of ADC, Signal Conditioning Amplifier and TI focus products for AC Analog Input Module.

Selecting a JESD204B Subclass

Date:
July 15, 2015

Duration:
05:14
This video discusses the three subclass modes in the JESD204B standard.  The pros and cons of operating in each subclass is discussed.

SAR and Delta-Sigma ADC Fundamentals

Date:
July 9, 2015

Duration:
02:35
A comparison between two of the most common precision analog-to-digital converter (ADC) architectures: successive approximation register and delta-sigma

SAR ADCs vs. Delta-Sigma ADCs: Different architectures for different application needs

Date:
October 13, 2015

Duration:
27:54
Are you choosing between ADC architectures for current or upcoming projects? Check out this webinar, aimed at helping you decide on the best product for your needs.
Understanding Sampling Rate vs Data Rate, Decimation (DDC) and Interpolation (DUC) Concepts in High Speed Data Converters

Sampling Rate vs Data Rate, Decimation (DDC) and Interpolation (DUC) Concepts in High Speed Data Converters

Date:
July 31, 2017

Duration:
18:41
Explore the differences between sample rate and data rate and use decimation or interpolation to decrease or increase the data rate.
205 Results
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