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Rohde & Schwarz: Demystifying 5G - Testing a 5G IF transceiver
Date:
Duration:
August 29, 2018
Duration:
06:34
The video explains the benefits of direct RF sampling for 5G systems, and tests a discrete transceiver for 5G NR based on the DAC38RF82 and the ADC12DJ3200.
Getting Best Performance From Your GSPS and RF Sampling ADC Designs
Date:
Duration:
May 8, 2017
Duration:
28:42
This video will talk about matching networks and clocking requirements for GSPS and RF Sampling ADC Inputs.
Bandwidth vs. Frequency - Subsampling Concepts
Date:
Duration:
July 31, 2017
Duration:
09:17
Learn more about subsampling concepts pertaining to bandwidth vs. frequency, including: Nyquist frequency, aliasing, under-sampling, and input bandwidth.
TX Signal Chain Implementation for Wide Band and High Frequency Signal Generation
Date:
Duration:
November 10, 2016
Duration:
13:45
The system design for an arbitrary waveform generator (AWG) and its functional blocks, including a discussion of the AWG amplifier path and design methodology.
The Impact of Jitter on Signal to Noise Ratio (SNR) for High-Speed Analog-to-Digital Converters (ADCs)
Date:
Duration:
July 31, 2017
Duration:
08:00
Considerations of Clock jitter, the impact on SNR, how to calculate it and minimize noise degradation for High-Speed Analog-to-Digital Converters.
Understanding Signal to Noise Ratio (SNR) and Noise Spectral Density (NSD) in High Speed Data Converters
Date:
Duration:
July 28, 2017
Duration:
14:32
Concepts of Signal to Noise Ratio and Noise Spectral Density; an example on how NSD is used to estimate the DAC output as it pertains to noise floor.
Introduction to the RF Sampling Architecture
Date:
Duration:
June 29, 2015
Duration:
03:21
Introduction to the RF sampling architecture in contrast to traditional direct conversion architectures typically used in existing transceivers.
Talk like a Pro - Data Flow
Date:
Duration:
July 15, 2015
Duration:
03:54
This video illustrates the block diagram of the JESD204B SERDES transceiver. The function of the individual blocks is described.
Get Your Clocks in Sync: Hardware Setup
Date:
Duration:
August 14, 2017
Duration:
02:31
This video demonstrates DEV_CLK skew between two clock outputs of the clocking reference design and the analog channel to channel skew between 2 ADC12DJ3200EVMs
Get Your Clocks in Sync: Software Setup
Date:
Duration:
August 7, 2017
Duration:
04:20
This video demonstrates the software setup of the Multi-Channel JESD204B 15 GHz Clocking Reference Design for DSO, Radar and 5G Wireless Testers
How to synchronize high speed multi-channel clocks?
This training explains how to synchronize high speed multi-channel clocks used in high-speed end equipment with multi-channel transceiver system.
Solving bandwidth limitations with high speed converters
Date:
Duration:
October 31, 2018
Duration:
13:40
Achieve wider bandwidth, lower latency and higher density with TI's high speed data converters.
Optimize Your RF Sampling ADC Receiver Performance with the Frequency & Sample Rate Planning Calculator
Date:
Duration:
April 6, 2018
Duration:
34:18
This video will go over what ADC SFDR's are, explain the concept of frequency planning and provide tools to help with RF sampling design.
Advanced JESD204B topics
This series explores advanced topics related to the JESD204B SerDes standard associated with extending the link length and multi-device synchronization.
General high-speed trainings
This series covers general updates on our high-speed signal chain portfolio.
High speed signal chain university
High speed signal chain university is your portal to relevant training material on high speed data converters and high speed amplifiers.
JESD204B video blog series
The JESD204B video blog series explores the basic concepts related to the JESD204B SerDes standard in relation to high-speed data converter products.
RF sampling
This series explores the new realm of RF sampling converters for use in high frequency, large bandwidth systems.
2018 South Asia Industrial webinar series
The topics will cover system design issues and solutions for building automation, power delivery and test & measurement.
IMS2015 - JOOS Demo
Date:
Duration:
August 28, 2015
Duration:
01:40
JESD204B is a common standard for implementing a SerDes interconnection between FPGA/Processor and the data converter.