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164 Results

KeyStone Multicore Navigator: Packet DMA

Date:
November 1, 2010
This module provides a detailed look at the infrastructure and functional aspects of the PKTDMA and provides information on programming PKTDMA through the use

KeyStone Multicore Navigator

Date:
November 1, 2010
This module provides an introduction to the architecture and functional components of the Multicore Navigator, which includes the Queue Manager Subsystem (QMSS

KeyStone Memory and Transport

This section provides information about the memory and transport architectures of the C66x DSP + ARM embedded processors.

KeyStone Memory and Cache

Date:
November 1, 2010
This module provides a detailed look at the KeyStone memory subsystem including the Multicore Shared Memory Controller (MSMC), local and shared memory/cache co

KeyStone Inter-Processor Communication (IPC)

Date:
December 1, 2012
This module provides an overview of the hardware and software that transports data and/or signals between threads of execution in KeyStone I C66x DSP multicore

KeyStone Instruction Set Architecture (ISA)

Date:
October 1, 2011
This module describes the differences between the TMS320C674x instruction set architecture and the TMS320C66x instruction set included in the KeyStone CorePac.

KeyStone II DSP+ARM SoC Architecture Overview

Date:
November 1, 2012
This module provides a high-level view of the device architecture, including the C66x DSP and ARM Cortex-A15 processors, memory and transport topologies, netwo

KeyStone I training: turbo decoder co-processor (TCP3D)

Date:
November 9, 2010

Duration:
45:16
Turbo Decoder Co-Processor (TCP3D) provides an overview of TCP3D including key features, modes, drivers, and configuration. Examples are provided.

KeyStone I training: power management

Date:
November 9, 2010

Duration:
24:26
Power Management provides an overview of the C66x power domain topology, power-saving features, power and clocking domains, powers states, and Smart Reflex.

KeyStone I training: network coprocessor (NETCP) overview

Date:
November 9, 2010

Duration:
04:20
Network Coprocessor (NETCP) Overview provides an introduction to the NETCP, which includes the Packet Accelerator (PA), Security Accelerator (SA), and Ethernet Subsystems.

KeyStone I training: NETCP - security accelerator (SA)

Date:
November 9, 2010

Duration:
15:45
NETCP Security Accelerator (SA)takes a look at the motivation behind the SA, the firmware and low level drivers, as well as a usage case for IPSec encryption and decryption.

KeyStone I training: NETCP - packet accelerator (PA)

Date:
November 9, 2010

Duration:
26:36
NETCP Packet Accelerator (PA) takes a look at the motivation behind the PA, the hardware, firmware and low level drivers, as well as a programming use case.

KeyStone I training: multicore software development kit (MCSDK) overview

Date:
November 9, 2010

Duration:
17:42
This session provides an introduction to and overview of the MCSDK.

KeyStone I training: multicore navigator overview

Date:
November 9, 2010

Duration:
36:36
Multicore Navigator Overview provides an introduction to the architecture and functional components of the Multicore Navigator, which includes the Queue Manager Subsystem (QMSS) and Packet DMA (PKTDMA).

KeyStone I training: multicore navigator - queue manager subsystem (QMSS)

Date:
November 9, 2010

Duration:
28:22
Multicore Navigator: Queue Manager Subsystem (QMSS) provides a detailed look at the functional elements of the QMSS and provides information on programming QMSS through the use of registers and low level drivers.

KeyStone I training: multicore navigator - packet DMA (PKTDMA)

Date:
November 9, 2010

Duration:
32:16
Multicore Navigator: Packet DMA (PKTDMA) provides a detailed look at the infrastructure and functional aspects of the PKTDMA and provides information on programming PKTDMA through the use of registers and low level drivers.

KeyStone I training: memory and cache

Date:
November 9, 2010

Duration:
01:01:07
CorePac & Memory Subsystem provides a detailed look at the C66x memory subsystem including the Multicore Shared Memory Controller (MSMC), local & shared memory/cache control, extended memory, and memory protection.

KeyStone I training: introduction to interprocessor communication (IPC)

Date:
November 9, 2010

Duration:
40:28
Introduction to Interprocessor Communication (IPC) provides an overview of the hardware and software that transports data and/or signals between threads of execution in the KeyStone family of C66x multicore devices.

KeyStone I training: instruction set architecture (ISA)

Date:
March 9, 2015

Duration:
30:57
C66x Instruction Set Architecture describes the differences between the TMS320C674x instruction set architecture and the TMS320C66x instruction set included in the KeyStone CorePac.

KeyStone I training: I/O interfaces

Date:
November 9, 2010

Duration:
22:05
I/O Interfaces provides an overview of selected external interfaces on the C66x devices including UART, I2C, SPI, TSIP and EMIF-A.
164 Results
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