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156 Results

Introduction to OpenCL: Why and When

Date:
July 29, 2019

Duration:
03:30
This video explains why and when to use OpenCL on Sitara AM57x & KeyStone 66AK2Ex, 66AK2Hx, and 66AK2Gx processors. 

Introduction to OpenCL: Processor SDK OpenCL Examples

Date:
July 29, 2019

Duration:
03:53
This video looks at OpenCL examples in the Processor SDK for Sitara AM57x & KeyStone 66AK2Ex, 66AK2Hx, and 66AK2Gx processors.

Processor SDK for TI Embedded Processors

This section provides an overview of the Processor SDK for Linux and RTOS for use on TI embedded processors.

Introduction to OpenCL on TI embedded processors

This technical series is an introduction to OpenCL Parallel Language for Heterogeneous Model support on Sitara AM57x & KeyStone 66AK2Ex, 66AK2Hx, and 66AK2Gx processors.  This training provides an overview down to specific coding examples.

Processor SDK Training Series

TI provides key runtime software components and documentation to further ease development. TI’s online training provides an introduction to the Processor SDK and how to use this software to start building applications on TI embedded processors.

The McASP Primer Training Series

This training series focuses on hardware design for the Multi-channel Audio Serial Port (McASP).  Before an engineer gets around to writing software for McASP, it has to be wired up properly. That is the focus of this McASP primer.

66AK2Gx Processors

The 66AK2Gx DSP + ARM processors are designed for automotive and consumer audio, industrial motor control, smart-grid protection and other high-reliability, real-time, compute-intensive applications. This training provides an overview of the device architecture and the processor cores. It also includes training related to voice and audio processing, as well as additional how-to video topics relevant to the EVMK2G evaluation module.

KeyStone I training: memory and cache

Date:
November 9, 2010

Duration:
01:01:07
C66x memory subsystem overview includes Multicore Shared Memory Controller (MSMC), local/shared memory/cache control, extended memory, and memory protection.

KeyStone ARM & DSP Multicore Device Training Series

This training series provides an in-depth look at KeyStone multicore SoC devices.

Debugging Common Application Issues with TI-RTOS

Date:
May 25, 2016

Duration:
25:26
This presentation shows how TI-RTOS helps a user debug the following common application issues: stack overflows, device exceptions, and memory mismanagement.
Tech Days

MCU and Processor

Learn more about TI microcontroller (MCU) and processor solutions.

Reduce design risk for Low Earth Orbit satellites and other New Space applications

When: October 8, 2019 2:00 pm
What is NewSpace? What does it mean for satellite design? Explore products that meet quality & reliability requirements for short space flights and LEO designs.

Voltage Regulator Design and Optimization for High-Current, Fast-Slew-Rate Load Transients

Designing to the tight voltage tolerances of today’s modern central processing units and field programmable gate arrays (FPGAs) is becoming more difficult as their current draw increases and becomes more dynamic. Getting the correct output capacitance mix to ensure first-time power-delivery success is no small feat with >100-A steps and slew rates in excess of 100 A/µs. Standard point-of-load design techniques no longer hold true; we need new methods to choose the output capacitance.

Understanding Transient Response In the Time and Frequency Domain

Date:
February 10, 2020

Duration:
05:10
Dive into how a regulator's transient response looks in both time and frequency

Output Capacitor Selection Using a Target Impedance Approach

Date:
February 10, 2020

Duration:
08:24
Study two techniques for selecting output capacitance to meet transient specs

DC Load Lines: How They Can Benefit Your Next Design

Date:
February 10, 2020

Duration:
05:04
Get top of the line performance out of your regulator by adding a DC Load Line
156 Results
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