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143 Results

KeyStone I training: multicore navigator - queue manager subsystem (QMSS)

Date:
November 9, 2010

Duration:
28:22
Multicore Navigator: Queue Manager Subsystem (QMSS) provides a detailed look at the functional elements of the QMSS and provides information on programming QMSS through the use of registers and low level drivers.

KeyStone I training: multicore navigator overview

Date:
November 9, 2010

Duration:
36:36
Multicore Navigator Overview provides an introduction to the architecture and functional components of the Multicore Navigator, which includes the Queue Manager Subsystem (QMSS) and Packet DMA (PKTDMA).

KeyStone I training: multicore software development kit (MCSDK) overview

Date:
November 9, 2010

Duration:
17:42
This session provides an introduction to and overview of the MCSDK.

KeyStone I training: NETCP - packet accelerator (PA)

Date:
November 9, 2010

Duration:
26:36
NETCP Packet Accelerator (PA) takes a look at the motivation behind the PA, the hardware, firmware and low level drivers, as well as a programming use case.

KeyStone I training: NETCP - security accelerator (SA)

Date:
November 9, 2010

Duration:
15:45
NETCP Security Accelerator (SA)takes a look at the motivation behind the SA, the firmware and low level drivers, as well as a usage case for IPSec encryption and decryption.

KeyStone I training: network coprocessor (NETCP) overview

Date:
November 9, 2010

Duration:
04:20
Network Coprocessor (NETCP) Overview provides an introduction to the NETCP, which includes the Packet Accelerator (PA), Security Accelerator (SA), and Ethernet Subsystems.

KeyStone I training: power management

Date:
November 9, 2010

Duration:
24:26
Power Management provides an overview of the C66x power domain topology, power-saving features, power and clocking domains, powers states, and Smart Reflex.

KeyStone I training: turbo decoder co-processor (TCP3D)

Date:
November 9, 2010

Duration:
45:16
Turbo Decoder Co-Processor (TCP3D) provides an overview of TCP3D including key features, modes, drivers, and configuration. Examples are provided.

TI's C553x DSPs - industry's lowest price and lowest power DSPs

Date:
September 16, 2011

Duration:
18:55
Imagine what you could do with a $2 DSP. You could finally add sophisticated signal processing power to audio and voice applications such as headsets, speakers, smart phone audio accessories and intelligence to your sensor applications at an unprecedented price. The TMS320C553x ultra-low-power DSP generation featuring the lowest power and lowest cost DSP in the industry, starting at $1.95/1 ku, are now available to enable you to do that and much more. Offering the industry’s lowest power with active power less than 0.15 mW/MHz at 1.05V and standby power less than 0.15 mW, these highly integrated processors enable developers to get DSP sophistication at a microcontroller price and power consumption.

KeyStone I Training: C665x SoC Overview

Date:
March 30, 2012

Duration:
10:26
The KeyStone C665x Architecture Overview provides a high-level view of the C665x device architecture, the processing and memory topologies, acceleration and interface improvements, as well as power saving and debug features. 

What is Arago? Learning more about TI support of the Yocto Project

Date:
March 19, 2013

Duration:
12:33
Are you starting to engage with a Mainline Linux design and looking to better understand the role that the Yocto Project plays? This training session will provide a high level overview of the Yocto Project and explain TI's engagement with the Arago distribution.

EE Live! Training: Fast DSP Development on the C5517 EVM

Date:
April 7, 2016

Duration:
17:17
Explore C5517 development platform capabilities through interactive setup and development. “10-minutes to ‘Hello World!’”

TI-RTOS Workshop Series 1 of 10 - Welcome

Date:
December 15, 2015

Duration:
46:23
<p><span style='font: 13px/18.57px "Open Sans", sans-serif; color: rgb(51, 51, 51); text-transform: none; text-indent: 0px; letter-spacing: normal; word-spacing: 0px; float: none; display: inline !important; white-space: nowrap; widows: 1; font-size-adjust: none; font-stretch: normal; background-color: rgb(255, 255, 255); -webkit-text-stroke-width: 0px;'>TI-RTOS Kernel 2-day Workshop - Part&nbsp;1 of 10</span></p>

TI-RTOS Update

Date:
March 18, 2015

Duration:
01:03:14
This session will include a combination of a presentation and a demo that introduce the latest TI-RTOS features to attendees, as well as giving them a more in-depth understanding of the product. We will begin with a presentation that overviews TI-RTOS features and device support with a special emphasis on new features that have been introduced in the areas of networking, power management, user interface, and toolchain compatibility. We will conclude with a demonstration of a TI-RTOS-based wireless networking application.

KeyStone I C667x DSP SoC Architecture Overview

Date:
March 1, 2012
This module provides a high-level view of the KeyStone I C667x device architecture, the processing and memory topologies, acceleration and interface improvements, as well as power saving and debug features for the KeyStone family of C66x multicore devices.

KeyStone I C665x DSP SoC Architecture Overview

Date:
June 1, 2016
This module provides a high-level view of the KeyStone I C665x device architecture, the processing and memory topologies, acceleration and interface improvements, as well as power saving and debug features.

KeyStone II DSP+ARM SoC Architecture Overview

Date:
November 1, 2012
This module provides a high-level view of the device architecture, including the C66x DSP and ARM Cortex-A15 processors, memory and transport topologies, networking and interface enhancements, as well as power saving and debug features for KeyStone II DSP+ARM multicore devices.

KeyStone C66x DSP CorePac Overview

Date:
January 1, 2012
This module discusses how high performance can be achieved within each C66x DSP core. Topics include C66x DSP CorePac architecture, Single Instruction Multiple Data (SIMD), memory access, and software pipelining.

KeyStone Instruction Set Architecture (ISA)

Date:
October 1, 2011
This module describes the differences between the TMS320C674x instruction set architecture and the TMS320C66x instruction set included in the KeyStone CorePac.

KeyStone Memory and Cache

Date:
November 1, 2010
This module provides a detailed look at the KeyStone memory subsystem including the Multicore Shared Memory Controller (MSMC), local and shared memory/cache control, extended memory, and memory protection.
143 Results